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DATA SHEET
MOS INTEGRATED CIRCUIT
PD70433
V55PITM 16-BIT MICROPROCESSOR
DESCRIPTION
The PD70433 (V55PI) is a microprocessor in which a 16-bit CPU, RAM, serial interface, parallel interface, A/D converter, timers, DMA controller, interrupt controller, etc., are integrated in a single chip. The V55PI is software-compatible with the PD70320 and 70330 (V25TM and V35TM) single-chip microcontrollers. The V55PI provides a migration path from the V25. It offers higher-level functions and higher performance, and is particularly suitable for control of data processing systems associated with mechanical control, including printer and facsimile. Detailed functions are described in the following user's manuals, which should be read when carrying out design work. * V55PI User's Manual Hardware * V55PI User's Manual Instruction : U10514E : U10231E
FEATURES
* Internal 16-bit architecture, selectable external data bus width (16/8 bits) * Software compatible with V20TM and V30TM (native mode) and V25 and V35 (includes additional instructions) * Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz) 125 ns/16 MHz (external 32 MHz) * Address space: 16M bytes: 1-Mbyte basic memory space 16-Mbyte extended memory space * Register file space (in on-chip RAM) : 512 bytes/16 register banks * I/O space : 64K bytes * Automatic wait control with memory space divided in variable sizes (max. 6 blocks) * I/O line (input ports: 11 bits, input/output ports: 42 bits) * DMA controller (DMAC): Max. 4-channel configuration possible * Four DMA transfer modes (single transfer, demand release, single step, burst) * Intelligent DMA modes 1 and 2 * Serial interface: 2 channels * Asynchronous mode (UART) or clocked mode (CSI) selectable * Parallel interface: 8 bits * Centronics data input/output and general-purpose data input/output * A/D converter (8 bits): 4 channels * Real-time output port: 4 bits x 2 channels or 8 bits x 1 channel * PMW (Pulse Width Modulation) output function : 8 bits
The information in this document is subject to change without notice. Document No. U11775EJ4V0DS00 (4th edition) Previous No. IC-8257 Date Published November 1996 P Printed in Japan
The mark
shows major revised points.
(c)
1995
PD70433
* Interrupt controller * Programmable priority (4 levels) * Three interrupt servicing methods Vectored interrupt function, register bank switching function, macro service function * 16-bit timer: 4 channels * Watchdog timer function * Software interval timer (16 bits) * Address field wait insertion function and RAS/CAS switchover timing generation function * DRAM and pseudo-SRAM refresh functions * Standby functions (STOP mode, HALT mode) * On-chip clock generator
APPLICATIONS
* Control of data processing systems using serial or parallel communication (Data processing terminals, printer, G3 facsimile, etc.)
ORDERING INFORMATION
Part Number Package 120-pin 120-pin 132-pin 132-pin 120-pin 120-pin Maximum Operating Frequency (MHz) 12.5 16 12.5 16 12.5 16
PD70433GD-12-5BB PD70433GD-16-5BB PD70433R-12 PD70433R-16 PD70433GJ-12-3EB PD70433GJ-16-3EB
plastic QFP (28 x 28 mm) plastic QFP (28 x 28 mm) ceramic PGA ceramic PGA plastic QFP (fine pitch) (20 x 20 mm) plastic QFP (fine pitch) (20 x 20 mm)
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PD70433
PIN CONFIGURATION (TOP VIEW) (1) 120-Pin Plastic QFP (28 x 28 mm), 120-pin plastic QFP (fine pitch) (20 x 20 mm)
PD70433GD-xx-5BB PD70433GJ-xx-3EB
OPEN DEX RAS IORD IOWR RD WRL WRH ASTB IC (L) D8/D16 GND VDD A23 A22 A21 A20 A19 A18 A17 A16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7
119 117 115 113 111 109 107 105 103 101 99 97 95 93 91 120 118 116 114 112 110 108 106 104 102 100 98 96 94 92 VDD BUSLOCK HLDAK HLDRQ READY POLL CLKOUT RESET WDTOUT VDD X1 X2 GND REFRQ P00 P01 P02 P03 P04 P05 P06 P07 GND P10/NMI P11/INTP0 P12/INTP1 P13/INTP2 P14/INTP3/TI P15/INTP4 P16/INTP5 1 90 2 89 3 88 4 87 5 86 6 85 7 84 8 83 9 82 10 81 11 80 12 79 13 78 14 77 15 76 16 75 17 74 18 73 19 72 20 71 21 70 22 69 23 68 24 67 25 66 26 65 27 64 28 63 29 62 30 61 313233343536373839404142434445464748495051525354555657585960 AD6 AD5 AD4 AD3 AD2 AD1 AD0 IC (H) GND VDD TCE1 TCE0 DMAAK1 DMAAK0 P81/DMARQ1 P80/DMARQ0 VDD P77/RTPT7 P76/RTPT6 P75/RTPT5 P74/RTPT4 P73/RTPT3 P72/RTPT2 P71/RTPT1 P70/RTPT0 GND AVDD AVREF P63/ANI3 P62/ANI2
Remark
IC: Internally Connected
Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 k). 2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 k). 3. No connection should be made to the OPEN pin.
P20/PWM P21/TO00 P22/TO01 P23/TO20 P24/TO21 P25/TO30 P30/TXD0/SB0/SO0 P31/RXD0/SB1/SI0 P32/TXC/SCK0 P33/CTS0 P34/TXD1/SO1 P35/RXD1/SI1 P36/SCK1/CTS1 VDD P40/PD0 P41/PD1 P42/PD2 P43/PD3 P44/PD4 P45/PD5 P46/PD6 P47/PD7 GND P50/DATASTB P51/ACK P52/BUSY VDD AVSS P60/ANI0 P61/ANI1
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PD70433
(2) 132-Pin Ceramic PGA
PD70433R-xx
Bottom View
14 13 12 11 10 9 8 7
Top View
Locator Pin
6 5 4 3 2 1
PNM
L
KJ
HGFEDC
BA
A
BCDEFGH
JK
L
MNP
Index Mark
Remark
The locator pin is not included in the pin count.
No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4
Signal Nane ANI1 AVSS ACK DATASTB PD6 PD4 PD1 NC SCK1/CTS1 TXD1/SO1 TXC/SCK0 TXD0/SB0/SO0 TO20 PWM AVDD ANI2 ANI0 BUSY
Port P61 -- P51 P50 P46 P44 P41 -- P36 P34 P32 P30 P23 P20 -- P62 P60 P52
No. B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8
Signal Name PD7 PD5 PD2 PD0 RXD1/SI1 RXD0/SB1/SI0 TO21 TO01 NC INTP3/TI RTPT1 AVREF NC NC VDD GND PD3 VDD
Port P47 P45 P42 P40 P35 P31 P24 P22 -- P14 P71 -- -- -- -- -- P43 --
No. C9 C10 C11 C12 C13 C14 D1 D2 D3 D12 D13 D14 E1 E2 E3 E12 E13 E14
Signal Name CTS0 TO30 TO00 NC INTP4 INTP0 RTPT2 GND ANI3 INTP5 INTP2 NMI RTPT5 RTPT3 RTPT0 INTP1 GND --
Port P33 P25 P21 -- P15 P11 P72 -- P63 P16 P13 P10 P75 P73 P70 P12 -- P06
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PD70433
No. F1 F2 F3 F12 F13 F14 G1 G2 G3 G12 G13 G14 H1 H2 H3 H12 H13 H14 J1 J2 J3 J12 J13 J14 K1 K2
Signal Nane RTPT7 RTPT6 RTPT4 --- --- --- NC DMARQ0 VDD --- --- --- DMARQ1 DMAAK0 DMAAK1 REFRQ --- NC TCE0 TCE1 GND VDD X2 GND VDD IC (H)
Port P77 P76 P74 P07 P05 P04 --- P80 --- P03 P02 P01 P81 --- --- --- P00 --- --- --- --- --- --- --- --- ---
No. K3 K12 K13 K14 L1 L2 L3 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2
Signal Name AD2 POLL WDTOUT X1 AD0 AD3 AD6 BUSLOCK READY RESET AD1 AD5 NC AD8 AD12 A16 A20 VDD WRH IORD NC NC HLDAK CLKOUT AD4 NC
Port --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
No. N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14
Signal Name AD9 AD11 AD14 A18 A21 A23 D8/D16 ASTB IOWR DEX VDD HLDRQ AD7 AD10 AD13 AD15 A17 A19 NC A22 GND IC (L) WRL RD RAS OPEN
Port --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- ---
Remark
IC: Internally Connected NC: Non-Connection
Notes 1. The IC (H) pin should be connected to VDD with an external resistor (1 to 10 k). 2. The IC (L) pin should be connected to GND with an external resistor (1 to 10 k). 3. No connection should be made to the OPEN pin.
5
6
TXD0/SB0/SO0 RXD0/SB1/SI0 CTS1/SCK1 PD0-PD7 ANI0-ANI3
INTERNAL BLOCK DIAGRAM
EXU VDD GND GENERAL REGISTERS & DATA MEMORY 512 BYTES
TXC/SCK0
DATASTB
TXD1/SO1
RXD1/SI1
BUSY
AVREF
CTS0
AVDD
AVSS
ACK
ALU
X2
X1
8
4 SYSTEM CONTROL RESET CLKOUT
MICRO SEQUENCE CONTROL MICRO ROM
UART/CSI
UART/CSI
PIU
8-BIT A/D
ASTB READY RD WRH WRL IORD IOWR RAS DEX D8/D16 BUSLOCK POLL HLDRQ HLDAK REFRQ A16-A23 AD0-AD15 DMARQ0 DMAAK0 TCE0 DMARQ1 DMAAK1 TCE1 DMAC * PWM * TO00 * TO20 * TO03 * WDTOUT * TO01 * TO21 * INTP0 * INTP1 * INTP2 * INTP3/TI * INTP4 * INTP5 BUS CONTROL & PREFETCH CONTROL PWM UNIT BCU PREFETCH QUEUE 6 BYTES DMA request
TIMER/ COUNTER UNIT WDT 4
PROGRAMMABLE INTERRUPT CONTROLLER
PORT
RTOP
284387678 6
PORT0 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORT7 PORT8
4
4
RTP4-RTP7
RTP0-RTP3
NMI
PD70433
PD70433
CONTENTS
1. PIN FUNCTIONS ....................................................................................................................................... 10
1.1 LIST OF PIN FUNCTION .................................................................................................................................... 10 1.1.1 Port Pins ................................................................................................................................................ 10 1.1.2 Non-Port Pins ........................................................................................................................................ 11
2. BLOCK CONFIGURATION ....................................................................................................................... 14
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 BUS CONTROL UNIT (BCU) ............................................................................................................................. 14 EXECUTION UNIT (EXU) ................................................................................................................................... 14 INTERRUPT CONTROLLER (INTC) ................................................................................................................. 14 DMA CONTROLLER (DMAC) ........................................................................................................................... 14 UART/CLOCKED SERIAL INTERFACE (UART/CSI) ...................................................................................... 14 PARALLEL INTERFACE UNIT (PIU) ................................................................................................................ 14 A/D CONVERTER UNIT (8-BIT A/D) ................................................................................................................ 14 TIMER/COUNTER UNIT (TCU) ......................................................................................................................... 14 PWM (PULSE WIDTH MODULATION) UNIT (PWM) ....................................................................................... 14 WATCHDOG TIMER (WDT) .............................................................................................................................. 14 PORTS (PORT) ................................................................................................................................................... 14 REAL-TIME OUTPUT PORT (RTOP) ................................................................................................................ 14 CLOCK GENERATOR (CG) .............................................................................................................................. 15 SOFTWARE INTERVAL TIMER (SIT) .............................................................................................................. 15
3. CPU FUNCTIONS ....................................................................................................................................... 16
3.1 3.2 FEATURES .......................................................................................................................................................... 16 REGISTERS ......................................................................................................................................................... 17 3.2.1 Register Banks ...................................................................................................................................... 17 3.2.2 3.2.3 3.2.4 3.2.5 3.3 3.4 3.5 General Registers (AW, BW, CW, DW) .............................................................................................. 19 Pointers (SP, BP) and Index Registers (IX, IY)................................................................................. 20 Segment Registers (PS, SS, DS0, DS1) ............................................................................................. 20 Extended Segment Registers (DS2, DS3) ......................................................................................... 21
3.2.6 Special Function Registers (SFR) ...................................................................................................... 22 PROGRAM COUNTER (PC) .............................................................................................................................. 23 PROGRAM STATUS WORDS (PSW) ............................................................................................................... 23 MEMORY SPACE ............................................................................................................................................... 24 3.5.1 3.5.2 3.5.3 3.5.4 Basic Memory Space ........................................................................................................................... 24 Extended Memory Space ..................................................................................................................... 25 Special Function Register Area .......................................................................................................... 26 Vector Table Area ................................................................................................................................. 34
3.6 3.7
REGISTER FILE SPACE ..................................................................................................................................... 36 I/O SPACE .......................................................................................................................................................... 38
4. BUS CONTROL FUNCTIONS .................................................................................................................... 39
4.1 4.2 WAIT FUNCTION ............................................................................................................................................... 39 REFRESH FUNCTION ........................................................................................................................................ 41 4.2.1 4.2.2 4.2.3 Refresh Mode Register (RFM)............................................................................................................. 41 Wait Control in Refresh Cycle ............................................................................................................ 41 Refresh Address ................................................................................................................................... 41
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PD70433
5. INTERRUPT FUNCTIONS ......................................................................................................................... 42
5.1 5.2 FEATURES ......................................................................................................................................................... 42 INTERRUPT RESPONSE METHODS ............................................................................................................... 45 5.2.1 5.2.2 5.2.3 Vectored Interrupts .............................................................................................................................. 45 Register Bank Switching Function .................................................................................................... 46 Macro Service Function ....................................................................................................................... 47
6. DMA FUNCTION (DMA CONTROLLER) ..................................................................................................48
6.1 FEATURES .......................................................................................................................................................... 48
7. SERIAL INTERFACE FUNCTIONS ...........................................................................................................50
7.1 7.2 7.3 7.4 FEATURES .......................................................................................................................................................... 50 PROTOCOLS ....................................................................................................................................................... 50 UART ................................................................................................................................................................... 51 7.3.1 Features ................................................................................................................................................. 51 CLOCKED SERIAL INTERFACE (CSI) ............................................................................................................... 52 7.4.1 Features ................................................................................................................................................. 52
8. PARALLEL INTERFACE FUNCTIONS .....................................................................................................53
8.1 FEATURES .......................................................................................................................................................... 53
9. TIMER FUNCTION ..................................................................................................................................... 55
9.1 9.2 9.3 FEATURES .......................................................................................................................................................... 55 TIMER UNIT CONFIGURATION ....................................................................................................................... 55 REAL-TIME OUTPUT PORT FUNCTION .......................................................................................................... 57 9.3.1 Real-Time Output Port Configuration ................................................................................................ 57 9.3.2 Real-Time Output Port Operation ...................................................................................................... 59
10. PWM UNIT .................................................................................................................................................. 61
10.1 10.2 FEATURES .......................................................................................................................................................... 61 PWM UNIT CONFIGURATION ......................................................................................................................... 61
11. WATCHDOG TIMER FUNCTION .............................................................................................................. 63
11.1 11.2 FEATURES .......................................................................................................................................................... 63 WATCHDOG TIMER CONFIGURATION AND OPERATION .......................................................................... 63
12. A/D CONVERTER FUNCTION .................................................................................................................. 64
12.1 FEATURES .......................................................................................................................................................... 64
13. STANDBY FUNCTION ............................................................................................................................... 66
13.1 13.2 HALT MODE ....................................................................................................................................................... 66 STOP MODE ....................................................................................................................................................... 67
14. CLOCK GENERATOR ............................................................................................................................... 68
14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION ......................................................................... 68
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PD70433
15. SOFTWARE INTERVAL TIMER FUNCTION ........................................................................................... 70
15.1 SOFTWARE INTERVAL TIMER CONFIGURATION ........................................................................................ 70
16. CODEC INSTRUCTION.............................................................................................................................. 71
16.1 16.2 16.3 FEATURES .......................................................................................................................................................... 71 MEMORY MAP ................................................................................................................................................... 74 PROCESSING FLOW ......................................................................................................................................... 76
17. INSTRUCTION SET .................................................................................................................................... 78
17.1 17.2 17.3 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35 ..................................................................... 78 INSTRUCTION SET OPERATIONS ................................................................................................................... 80 INSTRUCTION SET TABLE ............................................................................................................................. 105
18. ELECTRICAL SPECIFICATIONS ............................................................................................................128 19. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ................................................................... 158 20. PACKAGE DRAWINGS ........................................................................................................................... 159 21. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 162
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PD70433
1. PIN FUNCTIONS
1.1 1.1.1 LIST OF PIN FUNCTIONS Port Pins
Pin Name P00 to P07 Input/Output Input/output Function Port 0 Input/output specifiable bit-wise 8-bit input/output port NMI INTP0 INTP1 Input Port 1 7-bit input port INTP2 INTP3/TI INTP4 INTP5 PWM TO00 Port 2 Input/output specifiable bit-wise 6-bit input/output port TO01 TO20 TO21 TO30 TxD0/SB0/SO0 RxD0/SB1/SI0 Input/output P33 P34 P35 P36 P40 to P47 Port 4 Input/output specifiable bit-wise 8-bit input/output port Port 5 Input/output specifiable bit-wise 3-bit input/output port Port 6 Input/output specifiable bit-wise 4-bit input/output port Port 7 Input/output specifiable bit-wise 8-bit input/output port Input/output P80 P81 Port 8 Input/output specifiable bit-wise 2-bit input/output port Port 3 Input/output specifiable bit-wise 7-bit input/output port TxC/SCK0 CTS0 TxD1/SO1 RxD1/SI1 CTS1/SCK1 PD0 to PD7 Alternate Function
P10* P11 P12 P13 P14 P15 P16 P20 P21 P22 P23 P24 P25 P30 P31 P32
P50 P51 P52 P60 to P63 Input
DATASTB ACK BUSY ANI0 to ANI3
P70 to P77
RTP0 to RTP7 DMARQ0 DMARQ1
*
Unusable as general-purpose port (non-maskable interrupt)
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PD70433
1.1.2 (1)
Non-Port Pins Bus control pins
Input/ Output Alternate Function
Pin Name
Function
ASTB RD Output WRL
External bus cycle address strobe signal output in external bus External memory cycle data read strobe signal output in external bus External memory cycle lower byte data write strobe signal output in external bus External memory cycle upper byte data write strobe signal output in external bus Input External bus cycle ready signal input in external bus External bus cycle upper byte data enable signal output Output DRAM low address latch timing signal output Input Output External bus data bus width selection signal input External bus bus lock signal output Input of POLL signal (sampled in POLL instruction execution) Input External bus hold request signal input External bus hold acknowledge signal output Output Refresh pulse signal output 3-state input/output 3-state output External bus cycle address/data multiplex signal input/output in external bus External bus cycle address signal output in external bus External I/O cycle data read strobe signal output Output External I/O cycle data write strobe signal output DMA request signal input (channel 0) Input DMA request signal input (channel 1) DMA acknowledge signal output (channel 0) DMA acknowledge signal output (channel 1) Output --- DMA termination signal output (channel 0) DMA termination signal output (channel 1) P80 P81 ---
WRH READY DEX RAS D8/D16 BUSLOCK POLL HLDRQ HLDAK REFRQ AD0 to AD15
A16 to A23 IORD IOWR DMARQ0 DMARQ1 DMAAK0 DMAAK1 TCE0 TCE1
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PD70433
(2)
Other pins
Input/ Output GND potential Positive power supply --- A/D converter GND potential A/D converter analog power supply A/D converter reference voltage input --- Input System reset signal input Connection pins of crystal resonator/ceramic resonator for system clock generation. In case of external clock supply, input to X1 and leave X2 open. Internal system clock o output Output Watchdog timer overflow signal output Non-maskable interrupt request input *1 P10 P11 P12 P13 Input External interrupt request input *2 P14/TI P15 P16 External event clock input PWM output Output Timer unit output UART transmission data output Input Output UART reception data input UART transmission clock output P14/INTP3 P20 P21 to P25 P30/SB0/SO0 P31/SB1/SI0 P32/SCK0 P33 Input UART transmission enable signal input P36/SCK1 P30/TXD0/SO0 Input/output SBI transmission/reception data input/output P31/RXD0/SI0 Alternate Function
Pin Name
Function
GND VDD AVSS AVDD AVREF RESET X1 X2 CLKOUT WDTOUT NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 TI PWM TO00, TO01, TO20, TO21, TO30 TXD0 RXD0 TXC CTS0 CTS1 SB0 SB1 ---
* 1. Because NMI interrupt is unmaskable, NMI interrupt is always initiated by detecting a valid edge (when reading from port 1, the pin level is read). 2. By masking or disabling (IE = 0) these interrupts, these pins can be used as general-purpose input/output ports, respectively.
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PD70433
Pin Name SO0
Input/ Output
Function
Alternate Function P30/TXD0/SB0
Output SO1 SI0 Input SI1 SCK0
CSI transmission data output P34/TXD1 P31/RXD0/SB1 CSI reception data input P35/RXD1 P32/TXC CSI serial clock input/output P36/CTS1 Parallel interface -- Data input/output P40 to P47 P50 P51 P52 P60 to P63 P70 to P77
SCK1 PD0 to PD7 Input/output DATASTB ACK BUSY ANI0 to ANI3 RTP0 to RTP7 Input Output Parallel interface -- Data strobe signal Parallel interface -- Acknowledge signal Parallel interface -- Busy signal Analog input signal to A/D converter Real-time output port
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PD70433
2.
BLOCK CONFIGURATION
2.1 BUS CONTROL UNIT (BCU) The BCU performs control of the main bus. The BCU starts the necessary internal/external bus cycle on the basis of the physical address obtained from the execution unit (EXU). 2.2 EXECUTION UNIT (EXU) The EXU controls address calculation, arithmetic and logical operations, data transfer, etc., by means of a microprogram (firmware for controlling the microsequencer on the basis of decoded op code). The EXU contains 512 bytes of RAM (corresponding to the register file space). 2.3 INTERRUPT CONTROLLER (INTC)
The INTC services hardware interrupt requests generated by on-chip peripheral hardware and interrupt requests generated externally with vectored interrupts, bank switching, or macro service. It can also control the programmable 4level interrupt priority order, and can also perform multiprocessing control for interrupt. 2.4 DMA CONTROLLER (DMAC) The DMAC is a general-purpose DMA controller, capable of handling the 16M-byte memory space in a linear fashion. Operating modes comprise memory-to-memory transfer mode, intelligent DMA (ring buffer method and counter control method) mode, next address specification mode, and 2-channel operation. 2.5 UART/CLOCKED SERIAL INTERFACE (UART/CSI)
This block supports the asynchronous interface (UART) in which data synchronization is achieved by means of start/ stop bits, and the clocked serial interface (CSI), allowing either to be used. For the clocked serial interface there is a further choice of serial bus interface mode (SBI) or 3-wire serial I/O mode. 2.6 PARALLEL INTERFACE UNIT (PIU) This performs input/output using strobe signal synchronization in 8-bit units, and supports the Centronics interface and general-purpose parallel data communication functions. 2.7 A/D CONVERTER UNIT (8-BIT A/D) This is an A/D converter with 4 analog inputs, and provided with 4 A/D conversion result registers. 2.8 TIMER/COUNTER UNIT (TCU)
The timer/counter unit incorporates a 16-bit timer/counter, and can be used as an interval timer, free-running counter, or event counter. 2.9 PWM (PULSE WIDTH MODULATION) UNIT (PWM)
An 8-bit precision PWM (pulse width modulation) signal output function. 2.10 WATCHDOG TIMER (WDT) The WDT incorporates an 8-bit watchdog timer for detection of inadvertent program looping, system errors, etc. The WDTOUT pin is provided to give external notification of the generation of watchdog timer interrupts. 2.11 PORTS (PORT) 53 port pins are provided, allowing port pin and control pin functions to be selected. 2.12 REAL-TIME OUTPUT PORT (RTOP) This is a real-time output port which uses an interrupt from timer 0 as a trigger. It can output the contents of the 8-bit buffer register at programmable intervals in 4-bit or 8-bit units.
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PD70433
2.13 CLOCK GENERATOR (CG) The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins and supplies it as the CPU operating clock. 2.14 SOFTWARE INTERVAL TIMER (SIT) The SIT incorporates a 16-bit software interval timer as a software timer function and watch function timer. Interval interrupts can be set by input clock (count clock) selection and software timer/counter compare register setting.
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PD70433
3. CPU FUNCTIONS
The CPU of the V55PI is software upword compatible with the V20 and V30 (native mode), and the V25 and V35. 3.1 FEATURES * Software upward compatible with V20 & V30 (native mode) and V25 & V35 (includes additional instructions) * Minimum instruction cycle: 160 ns/12.5 MHz (external 25 MHz clock) 125 ns/16 MHz (external 32 MHz clock) * Address space: 16M bytes 1M-byte basic memory (program) space 16M-byte extended memory (data) space
* Register file space (in on-chip RAM): 512 bytes/16 register banks * I/O space: 64K bytes * Register configuration (compared with V20/V30 and V25/V35)
Item Extended segment register Register bank Mode flag Register bank flags PSW Input/output instruction trap flag User flag None None IBRK F0, F1 240 bytes (memory mapping onto FFF00H to FFFEFH) IBRK None 496 bytes (memory mapping onto FFE00H to FFFEFH) V20, V30 None None MD None V25, V35 None 8 banks (in memory space) None RB0 to RB2 V55PI DS2, DS3 16 banks (in register file space) None RB0 to RB3
Special function register area
None
* Internal 16-bit architecture, switchable external data bus width (16/8 bits) * Automatic wait control with memory divided in variable sizes (max. 6 blocks) * Programmable wait function * Wait function using READY pin * Refresh function * Automatic generation of refresh cycle (RAS only) * RAS pin functions RAS pin RD, WRH, WRL pins ASTB pin DRAM RAS timing DRAM CAS timing DRAM row/column address switching timing
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PD70433
3.2 REGISTERS The V55PI CPU has general register sets compatible with the V20 and V30 (native mode), and the V25 and V35. The general register sets are mapped onto the register file space. These general register sets are also used as on-chip RAM, and there can be a maximum of 16 register sets in bank form. In addition, the V55PI has various special function registers for controlling on-chip peripheral hardware. These special function registers are mapped onto memory space addresses 0FFE00H to 0FFFEFH. 3.2.1 Register Banks
The general register sets are mapped onto the register file space (in on-chip RAM). The general register sets are used in a bank arrangement; each bank consists of 32 bytes and up to 16 banks can be set. The CPU normally uses register bank 15 for program execution, and it is possible to switch to another bank automatically by means of maskable hardware interrupt or software interrupt (BRKCS instruction). It is possible to return from the switchedto register bank to the original register bank by means of the instruction for returning from an interrupt (RETRBI). The register bank configuration is shown in Figure 3-1. The general register sets are mapped onto the area with an offset of (+08H) to (+1FH) from the start address of each register bank. The word address from the start in a register bank is the extended segment register (DS2) area. The vector PC/DS3 area is used to set the value to be loaded into the PC when the register bank is switched, that is, the offset value of the start address of the interrupt service routine. This area is also used as the extended segment register (DS3) area. The PSW save area is used to save the PSW when the register bank is switched, and the PC save area is used to save the PC when the register bank is switched. After a reset, register bank 15 is selected automatically. Also, segment register initialization after a reset is performed for register bank 15 only. The register file space onto which these general register sets are mapped can also be accessed as data memory by addition of a special prefix instruction (IRAM:) to a memory manipulation instruction. Of the 16 set register banks, banks 0 and 1 have macro service channels (parameter and work area for macro service) allocated in duplicate.
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PD70433
Figure 3-1. Register Bank Configuration
Register File Space (512 bytes)
+00H 000H Register Bank 020H 1 040H 2 060H 3 080H 4 0A0H 5 0C0H 6 0E0H 7 100H 8 120H 9 140H 10 160H 11 180H 12 1A0H 13 1C0H 14 1E0H 15 1FFH +1EH AW AH AL +1CH CH +1AH DW DH CW CL DL +18H BH +16H SP BW BL +14H BP +12H IX +10H IY +0EH DS1 +0CH PS +0AH SS +08H DS0 +06H PC Save +04H PSW Save 0 +02H Vector PC/DS3 DS2 15 87 0
(Offset from the starting address of each register bank)
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PD70433
3.2.2 General Registers (AW, BW, CW, DW) There are four 16-bit general registers. In addition to being accessed as 16-bit registers, these registers can also be accessed as 8-bit registers by dividing each register into upper and lower 8-bit halves (AH, AL, BH, BL, CH, CL, DH, DL). These registers are used as 8-bit or 16-bit registers with a wide range of instructions including transfer, arithmetic and logical operation instructions. Each register is also used as the default register for specific instruction processing, as shown below. AW : Word multiplication/division, word input/output, data conversion AL : Byte multiplication/division, byte input/output, BCD rotation, data conversion AH : Byte multiplication/division BW : Data conversion CW : Loop control branch, repeat prefix CL : Shift instructions, rotate instructions, BCD operations DW : Word multiplication/division, indirect addressing input/output These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number x 32).
Table 3-1. General Register Offsets
Register
Offset
Register AL
Offset 1EH 1FH 18H 19H 1CH 1DH 1AH 1BH
AW
1EH AH BL
BW
18H BH CL
CW
1CH CH DL
DW
1AH DH
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PD70433
3.2.3 Pointers (SP, BP) and Index Registers (IX, IY) These are 16-bit registers used as base pointers or index registers in memory accesses using based addressing (BP), indexed addressing (IX, IY), based indexed addressing (BP, IX, IY), etc. The SP is also used as the pointer in stack operations. As with general registers, these are used with transfer instructions, arithmetic operation instructions, etc., but in this case they cannot be used as 8-bit registers. Each register is also used as the fixed address pointer for specific instruction processing, as shown below. SP : Stack manipulation IX : Block transfers, BCD operation source side address specification IY : Block transfers, BCD operation destination side address specification These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number x 32). Table 3-2. Pointer and Index Register Offsets
Register SP BP IX IY
Offset 16H 14H 12H 10H
3.2.4 Segment Registers (PS, SS, DS0, DS1) The CPU manages the 1M-byte basic memory space by dividing it into 64K-byte units. The CPU specifies the start address of each segment with a segment register, and uses another register or effective address for the specification of phyiscal address, with the relative address from the start address as the offset. The physical address is created as shown below. Segment Register 4-Bit Fixed
x
x
x
x
0
H
....
Segment Start Address
+
0
x
x
x
x
H
....
Offset Value
x
x
x
x
x
H
.....
Physical Address (20 Bits)
There are four segment registers: PS (Program Segment), SS (Stack Segment), DS0 (Data Segment 0), and DS1 (Data Segment 1). The respective segments are used in the following cases. PS : Program fetch SS : Stack manipulation instructions, addressing using BP as base register DS0 : General variable accesses, source block data accesses such as block transfer instructions, etc. DS1 : Destination block data accesses such as block transfer instructions, etc.
20
PD70433
However, using a segment override prefix instruction makes it possible for access of general variables to change from DS0 to another segment register. Also, in addressing which uses BP as the base register, another segment register can be used instead of SS. Example MOV MOV MOV AW, 1000H DS1 : AW BL, DS1, BYTE PTR [IX]; DSI : Byte data read from IX
When a reset is performed, PS of register bank 15 is initialized to FFFFH, and SS, DS0 and DS1 are initialized to 0000H. These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number x 32). Table 3-3. Segment Register Offsets
Register DS0 DS1 SS PS
Offset 08H 0EH 0AH 0CH
3.2.5 Extended Segment Registers (DS2, DS3) In addition to the segment registers for accessing the 1M-byte basic memory space, the V55PI is provided with extended segment registers which specify the start address of each 64K-byte segment of the 16M-byte extended memory space. There are two extended segment registers, DS2 (Data Segment 2) and DS3 (Data Segment 3), which are used as shown below. DS2: Extended memory space general variable accesses (by segment override prefix instructions), source block data accesses in extended memory space block transfer instructions, etc. DS3: Extended memory space general variable accesses (by segment override prefix instructions), destination block data accesses in extended memory space block transfer instructions, etc. The data access using an extended semgnet register is performed by using the segment override prefix. Especially, in the block transfer instruction, DS2 and DS3 can be specified simultaneously by segment override prefix. (In this case, the order for DS2 and DS3 is optional.) Example REP DS2: DS3: MOVBKW ; Word memory block transfer from DS2 : IX to DS3 : IY. The CPU specifies the start address of each segment with an extended segment register, and performs an access by using another register or effective address for the specification of physical address, with the relative address from the start address as the offset value. The physical address is created as shown in the next page.
21
PD70433
Extended Segment Register 8-Bit Fixed
x
x
x
x
0
0
H
...
Segment Start Address
+
0
0
x
x
x
x
H
...
Offset Value
x
x
x
x
x
x
H
...
Physical Address (24 Bits)
When a reset is performed, DS2 and DS3 of register bank 15 are initialized to 0000H. These registers are mapped onto the register file space (in on-chip RAM). The address is the value obtained by adding the offset for each register to (register bank number x 32).
Table 3-4. Extended Segment Register Offsets
Register DS2 DS3 Offset 00H 02H (Also used as vectored PC)
3.2.6
Special Function Registers (SFR)
The V55PI has a group of registers with the function of controlling on-chip peripheral hardware. A number of registers are provided according to the type of cotrol for each peripheral hardware unit, and the actual operation can be set using the individual bits in the registers. These registers are mapped onto the memory space, and are read and written to using the same method as for ordinary memory (see 3.5.3 "Special Function Register Area"). Example MOV MOV MOV AW, 0FFE0H DS1, AW BL, DS1 : BYTE PTR [1EFH]; 0FFE0H : 1EFH (PRC register) Read
There are also two instructions, BTCLR and BTCLRL, which are only valid for special function registers. Of these, BTCLRL is an instruction newly provided in the V25 or V35. The BTCLR instruction is valid for registers in the upper 240 bytes (0FFF00H to 0FFFEFH) of the special function register area, and the BTCLRL instruction is valid for registers in the lower 256 bytes (0FFE00H to 0FFEFFH).
22
PD70433
3.3 PROGRAM COUNTER (PC) This is a 16-bit binary counter which holds the offset value of the program memory address on which the CPU is to perform execution. The PC is incremented each time an instruction code is fetched from the instruction queue, and is also loaded with the new location address value when a branch, call, return or break instruction is executed. When a reset is performed, 0000H is loaded into the PC. Because the PS register is initialized to FFFFH in a reset, after a reset the CPU begins execution at physical address 0FFFF0H. 3.4 PROGRAM STATUS WORDS (PSW) The PSW consists of 6 status flags and 5 control flags. * Status flags * V (Overflow) * S (Sign) * Z (Zero) * AC (Auxiliary Carry) * P (Parity) * CY (Carry) * Control flags
...Overflow detection flag ...Sign bit detection flag ...All zero detection flag ...4-bit carry/borrow detection flag ...Parity detection flag ...Carry/borrow detection flag
* RB0 to RB3 (Register Banks 0 to 3) ...Register bankspecification flags * DIR (Direction) ...Block transfer/input/output instruction direction control flag * IE (Interrupt Enable) * BRK (Break) * IBRK (I/O Break) ...Interrupt enabled state control flag ...Single-step interrupt control flag ...Input/output instruction trap control flag
The status flags are set (1) or reset (0) automatically according to the result (data value) of execution of various kinds of instructions. The CY flag can be directly set, reset or inverted by an instruction. The control flags are set or reset by instructions, and control the operation of the CPU. The IE and BRK flags are always reset when interrupt servicing is initiated. The contents of the PSW can be saved to and restored from the stack by the PUSH and POP instructions. However, when the contents are restored by the POP PSW instruction, bits 12 to 15 (RB0 to RB3) are not returned to the PSW. The low-order 8 bits of the PSW can also be saved to or restored from the AH register by an MOV instruction. The PSW bit configuration is shown below.
15 RB3 14 RB2 13 RB1 12 RB0 11 Y 10 DIR 9 IE 8 BRK 7 S 6 Z 5 0 4 AC 3 0 2 P 1 IBRK 0 CY
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3.5
MEMORY SPACE
The V55PI has a 16M-byte memory space. Of this, using lowest 1M bytes (000000H to 0FFFFFH) as the basic memory space, the 16M bytes including the basic memory space (000000H to FFFFFFH) can be accessed as the extended memory space. The basic memory space can be accessed using the segment registers (PS, SS, DS0, DS1) in the same way as in the V25 and V35. The extended memory space can be accessed using the extended segment registers (DS2, DS3), and has the basic memory space mapped onto the lowest 1M bytes. See 3.2.4 "Segment Registers (PS, SS, DS0, DS1)" and 3.2.5 "Extended Segment Registers (DS2, DS3)" for the physical addresses. The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which specific functions are allocated such as on-chip peripheral hardware registers, control registers, etc., and these are manipulated by memory accesses. In addition, independent of these, there is a 512-byte register file space (in on-chip RAM). In addition to being accessed by using register manipulation instructions as in the V25 and V35, the register file space can also be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation in. Figure 3-2. Memory Space
000000H Vector Area 003FFH
Basic Memory Space (1M Bytes)
0FFFFFH 100000H Special Function Register Area (On-Chip Area)
FFE00H FFFEFH
Extended Memory Space (16M Bytes)
FFFFFFH
3.5.1 Basic Memory Space The memory space comprises a 1M-byte basic memory space and 16M-byte extended memory space. The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space. The 1M-byte basic memory space is shown in Figure 3-3. Conditions for accessing the basic memory space by software are the same as for the V20/V30 and V25/V35. A basic memory space physical address is specified by the segment start address indicated by the segment register (PS, SS, DS0, DS1) and the offset value from the segment start position indicated by another register or immediate data. The basic memory space has the vectored interrupt vector area and special function register area mapped onto it. For an area in which special function registers are mapped, data accesses cannot be made to external memory (program fetches are possible.)
24
PD70433
Figure 3-3. Basic Memory Space
000000H Vector Area 003FFH 00000H
1M Bytes
FFE00H Spaecial Function Register Area (Internal Area) FFFEFH 0FFFFFH
0FFF0H to 0FFFFFH is a program area used for the system boot, and PS and PC become 0FFFH and 0H, respectively, therefore the program execution starts from 0FFFF0H. 3.5.2 Extended Memory Space
The 16M-byte extended memory space is shown in Figure 3-4. The only accesses that can be performed on the extended memory space are data accesses. The basic memory space is mapped onto the lowest 1M bytes (000000H to 0FFFFFH) of the extended memory space, and can be accessed using the segment registers PS, SS, DS0 and DS1. Data accesses can be performed in the extended memory space using the extended segment registers DS2 and DS3. With DS2 and DS3 it is possible to use a specification as a segment override prefix instruction added to a memory manipulation instruction. An extended memory space physical address is specified by the segment start address indicated by the extended segment register and the offset value from the segment start position indicated by another register or immediate data. If the generated address indicates the lowest 1M-byte area (000000H to 0FFFFFH), the basic memory space is accessed.
25
PD70433
Figure 3-4. Extended Memory Space
000000H 00000H 003FFH
Vector Area
1M Bytes
FFE00H FFFEFH 0FFFFFH 100000H 16M Bytes Spaecial Function Register Area (Internal Area)
FFFFFFH
3.5.3 Special Function Register Area The 496-byte space 0FFE00H to 0FFFEFH has mapped onto it a group of registers to which functions such as on-chip peripheral hardware operation specification, status monitoring, etc., are assigned. Program fetches cannot be performed from these areas. Special function register manipulation is performed by accesses by means of memory manipulation instructions. If the special function register area is accessed, RD, WRH, WRL, IORD, IOWR and other control signals do not become active. A list of special function registers is given in Table 3-5. The meaning of the items in the table is explained below. * Symbol ............................ The symbol used to indicate the special function register name. Corresponds to the operand description format (symbol name) in a memory manipulation instruction. * R/W ................................. Indicates whether this special function register is read/write enabled. R/W : Read/write enabled R : Read only W : Write only * Manipulation Method ..... Indicates which of the following can be used on the register: bit manipulation, 8-bit manipulation, 16-bit manipulation, 32-bit manipulation. * RESET ............................ Indicates the status of the register after RESET input. Note Addresses which are not listed are the reserved area, therefore, they should not be accessed by the user program.
26
Table 3-5. Special Function Registers (1/7) Manipulable Bit Units 1 Bit
0FFE00H 0FFE02H 0FFE04H 0FFE06H 0FFE10H 0FFE18H 0FFE19H 0FFE1AH 0FFE1CH 0FFE1DH 0FFE20H 0FFEC0H 0FFEC1H 0FFEC2H 0FFEC3H 0FFEC4H 0FFEC5H 0FFEC9H 0FFECAH 0FFECBH 0FFECCH 0FFECDH A/D conversion result register 0 A/D conversion result register 1 A/D conversion result register 2 A/D conversion result register 3 Parallel interface buffer Parallel interface control register 0 Parallel interface control register 1 Parallel interface status register Parallel interface acknowledge interval register 1 Parallel interface acknowledge interval register 2 A/D converter mode register Interrupt mask flag register 0 (low) MK0 Interrupt mask flag register 0 (high) Interrupt mask flag register 1 (low) MK1 Interrupt mask flag register 1 (high) In-service priority register Interrupt mode control register Interrupt request control register 09 Interrupt request control register 10 Interrupt request control register 11 Interrupt request control register 12 Interrupt request control register 13 ISPR IMC IC09 IC10 IC11 IC12 IC13 MK1H R/W R R/W R/W R/W R/W R/W R/W MK0H MK1L R/W R/W ADCR0 ADCR1 ADCR2 ADCR3 PAD PAC0 PAC1 PAS PAI1 PAI2 ADM MK0L R R R R R/W *1 R/W R/W R/W *2 W W R/W R/W
Address
Special Function Register Name
Symbol
R/W
After Reset
Undefined Undefined Undefined Undefined Undefined 90H 03H 40H Undefined Undefined 00H
8 Bits 16 Bits 32 Bits
* *
* * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * *
* *
FFH FFH FFH FFH 00H 80H 43H 43H 43H
PD70433
43H 43H
* 1. Varies according to input/output mode. 2. Some bits R, others R/W (possible).
27
28
Address
0FFECEH 0FFED0H 0FFED1H 0FFED2H 0FFED3H 0FFED4H 0FFED5H 0FFED6H 0FFED7H 0FFED8H 0FFED9H 0FFEDAH 0FFEDBH 0FFEDCH 0FFEDDH 0FFEDEH 0FFEDFH 0FFEE0H 0FFEE4H 0FFEE5H 0FFF00H 0FFF01H 0FFF02H 0FFF03H Interrupt request control register 14 Interrupt request control register 16 Interrupt request control register 17 Interrupt request control register 18 Interrupt request control register 19 Interrupt request control register 20 Interrupt request control register 21 Interrupt request control register 22 Interrupt request control register 23 Interrupt request control register 24 Interrupt request control register 25 Interrupt request control register 26 Interrupt request control register 27 Interrupt request control register 28 Interrupt request control register 29 Interrupt request control register 30 Interrupt request control register 31 Interrupt request control register 32 Interrupt request control register 36 Interrupt request control register 37 Port 0 Port 1 Port 2 Port 3
Table 3-5. Special Function Registers (2/7) Manipulable Bit Units 1 Bit
IC14 IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC23 IC24 IC25 IC26 IC27 IC28 IC29 IC30 IC31 IC32 IC36 IC37 P0 P1 P2 P3 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W
Special Function Register Name
Symbol
R/W
After Reset
43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H 43H
8 Bits 16 Bits 32 Bits
* * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * *
PD70433
Undefined Undefined Undefined Undefined
Table 3-5. Special Function Registers (3/7) Manipulable Bit Units 1 Bit
0FFF04H 0FFF05H 0FFF06H 0FFF07H 0FFF08H 0FFF0CH 0FFF0EH 0FFF10H 0FFF12H 0FFF13H 0FFF14H 0FFF15H 0FFF17H 0FFF18H 0FFF22H 0FFF23H 0FFF24H 0FFF25H 0FFF27H 0FFF28H 0FFF2CH 0FFF2DH 0FFF2EH 0FFF2FH Port 4 Port 5 Port 6 Port 7 Port 8 Port read control register Real-time output port Port 0 mode register Port 2 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 7 mode register Port 8 mode register Port 2 mode conrol register Port 3 mode control register Port 4 mode control register Port 5 mode control register Port 7 mode control register Port 8 mode control register Real-time output port control register Real-time output port delay specification register Port 7 buffer (low) Port 7 buffer (high) P4 P5 P6 P7 P8 PRDC RTP PM0 PM2 PM3 PM4 PM5 PM7 PM8 PMC2 PMC3 PMC4 PMC5 PMC7 PMC8 RTPC RTPD P7L P7H R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Address
Special Function Register Name
Symbol
R/W
After Reset
Undefined Undefined Undefined Undefined Undefined 00H Undefined FFH FFH FFH FFH FFH FFH FFH 00H 00H 00H 00H 00H 00H
8 Bits 16 Bits 32 Bits
* * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * *
PD70433
40H Undefined Undefined Undefined
29
30
Address
0FFF30H 0FFF31H 0FFF32H 0FFF33H 0FFF34H 0FFF35H 0FFF40H 0FFF42H 0FFF44H 0FFF46H 0FFF48H 0FFF4AH 0FFF4CH 0FFF4EH 0FFF50H 0FFF52H 0FFF54H 0FFF58H 0FFF5AH 0FFF5CH 0FFF5EH 0FFF60H 0FFF64H Timer control register 0 Timer control register 1 Timer output control register 0 Timer output control register 1 External interrupt mode register 0 External interrupt mode register 1 Timer register 0 Timer register 1 Timer register 2 Timer register 3 Timer capture register 00 Timer capture register 01 Timer compare register 00 Timer compare register 01 Timer capture register 10 Timer compare register 10 Timer compare register 11 Timer compare register 20 Timer compare register 21 Timer compare register 22 Timer compare register 23 Watchdog timer mode register Timer compare register 30
Table 3-5. Special Function Registers (4/7) Manipulable Bit Units 1 Bit
TMC0 TMC1 TOC0 TOC1 INTM0 INTM INTM1 TM0 TM1 TM2 TM3 CT00 CT01 CM00 CM01 CT10 CM10 CM11 CM20 CM21 CM22 CM23 WDM CM30 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W* R/W R/W R/W R/W R/W R/W
Special Function Register Name
Symbol
R/W
After Reset
00H 00H 00H 00H 00H 00H 00H 00H 00H 00H Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
8 Bits 16 Bits 32 Bits
* * * * * *
* * * * * *
* * * * * * * * * * * * * * * * * *
PD70433
Undefined 00H
*
* *
Undefined
*
WDT can only be written to by the RSTWDT instruction (8-bit unit only).
Table 3-5. Special Function Registers (5/7) Manipulable Bit Units 1 Bits
0FFF66H 0FFF6CH 0FFF6DH 0FFF70H 0FFF71H 0FFF72H 0FFF73H 0FFF74H 0FFF75H 0FFF76H 0FFF78H 0FFF79H 0FFF7AH 0FFF7BH 0FFF7CH 0FFF7DH 0FFF7EH 0FFF7FH 0FFF80H 0FFF82H Timer compare register 31 PWM register PWM control register Transmit baud rate generator register 0 Receive baud rate generator register 0 Prescaler register 0 UART mode register 0 / clocked serial interface mode register 0 UART status register 0 / SBI control register 0 UART transmit buffer 0 / clocked serial I/O shift register 0 Receive buffer 0 Transmit baud rate generator register 1 Receive baud rate generator register 1 Prescaler register 1 UART mode register 1 / clocked serial interface mode register 1 UART status register 1 UART transmit buffer 1 / clocked serial I/O shift register 1 Receive buffer 1 Protocol selection register Terminal counter 0 (low) Terminal counter 0 (high) CM31 PWM PWMC TXBRG0 RXBRG0 PRS0 UARTM0/CSIM0 UARTS0/SBIC0 TXB0/SIO0 RXB0 TXBRG1 RXBRG1 PRS1 UARTM1/CSIM1 UARTS1 TXB1/SIO1 RXB1 ASP TC0 TC0L TC0H R/W R/W R/W R/W R/W R/W R/W *1/*2 W R R/W R/W R/W R/W *1/*2 W R R/W R/W R/W
Address
Special Function Register Name
Symbol
R/W
After Reset
8 Bits 16 Bits 32 Bits
* * * * * * () * () * * * * () * () * * * * * * * * * * * * * * * * * * * * * * *
Undefined 00H 00H Undefined Undefined 00H 00H 00H Undefined Undefined Undefined Undefined 00H 00H 00H Undefined Undefined 00H Undefined Undefined
PD70433
* 1. Some bits R, others R/W. 2. R or W in bit units. Remark ( ): Depends on the mode.
31
32
Address
0FFF84H 0FFF86H 0FFF88H 0FFF8AH 0FFF8CH 0FFF8EH 0FFF90H 0FFF92H 0FFF94H 0FFF96H 0FFF9CH 0FFF9DH 0FFF9EH 0FFFA0H 0FFFA2H 0FFFA4H 0FFFA6H 0FFFA8H 0FFFAAH 0FFFACH 0FFFAEH 0FFFB0H 0FFFB2H Terminal counter modulo register 0 (low) Terminal counter modulo register 0 (high) DMA up/down counter 0 (low) DMA up/down counter 0 (high) DMA compare register 0 (low) DMA compare register 0 (high) DMA memory address register 0 (low) DMA memory address register 0 (high) DMA read/write pointer 0 (low) DMA read/write pointer 0 (high) DMA mode register 0 DMA control register 0 DMA status register Terminal counter 1 (low) Terminal counter 1 (high) Terminal counter modulo register 1 (low) Terminal counter modulo register 1 (high) DMA up/down counter 1 (low) DMA up/down counter 1 (high) DMA compare register 1 (low) DMA compare register 1 (high) DMA memory address register 1 (low) DMA memory address register 1 (high)
Table 3-5. Special Function Registers (6/7) Manipulable Bit Units 1 Bit
TCM0L TCM0 TCM0H UDC0L UDC0 UDC0H DCM0L DCM0 DCM0H MAR0L MAR0 MAR0H DPTC0L DPTC0 DPTC0H DMAM0 DMAC0 DMAS TC1L TC1 TC1H TCM1L TCM1 TCM1H UDC1L UDC1 UDC1H DCM1L DCM1 DCM1H MAR1L MAR1 MAR1H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Special Function Register Name
Symbol
R/W
After Reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined E0H 00H 00H
8 Bits 16 Bits 32 Bits
* * * * * * ** * * * * * * * * *
* * * * * * * * * *
* * * * *
* * * * * * * * * *
* * * * *
Undefined Undefined Undefined Undefined Undefined Undefined Undefined
PD70433
Undefined Undefined Undefined
*
Bit clear operation possible.
Table 3-5. Special Function Registers (7/7) Manipulable Bit Units 1 Bit
0FFFB4H 0FFFB6H 0FFFBCH 0FFFBDH 0FFFE0H 0FFFE2H 0FFFE8H 0FFFE9H 0FFFEAH 0FFFECH 0FFFEEH 0FFFEFH DMA read/write pointer 1 (low) DPTC1 DMA read/write pointer 1 (high) DMA mode register 1 DMA control register 1 Software timer/counter Software timer/counter compare register Programmable wait control register 0 Programmable wait control register 1 Memory block control register Refresh mode register Standby control register Processor control register DMAM1 DMAC1 STC STMC PWC0 PWC1 MBC RFM STBC PRC DPTC1H R/W R/W R/W R R/W R/W R/W R/W R/W R/W *1 R/W DPTC1L R/W
Address
Special Function Register Name
Symbol
R/W
After Reset
Undefined Undefined E0H 00H
8 Bits 16 Bits 32 Bits
* * * * * * * *
* * * * * * * * *
* * * *
*
Undefined FFFFH EAH AAH FCH 77H Undefined *2 EEH
*1 The SFB bit of the standby control register can be set (1) by instruction, but cannot be cleared (0). (Only '1' can be written.) *2 After power-on reset: 00H, otherwise: no change
PD70433
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PD70433
3.5.4 Vector Table Area The 1K-byte area 00000H to 003FFH in the memory space holds 256 vectors (4 bytes used per vector) for the start addresses of interrupt routines initiated by interrupt requests, break instructions, etc. In the initial state, vectors 0 to 47 are reserved as V55PI family dedicated on-chip peripheral and software interrupt vectors. For vectors 8 to 47, the vector address of hardware interrupts except NMI can be changed by means of bits V0 and V1 of the interrupt mode control register (IMC). Vector 0 Vector 1 Vector 2 Vector 3 Vector 4 Vector 5 Vector 6 Vector 7 (00000H) (00004H) (00008H) (0000CH) (00010H) (00014H) (00018H) (0001CH) : Divide error : Single step : NMI instruction : BRK 3 instruction : BRKV instruction : CHKIND instruction : Input/output instruction : FPO instruction/exception trap
When V1 = V0 = 0 : Vector 8 Vector 9 Vector 10 Vector 11 Vector 12 Vector 13 Vector 14 Vector 15 Vector 16 Vector 17 Vector 18 Vector 19 Vector 20 Vector 21 Vector 22 Vector 23 Vector 24 Vector 25 Vector 26 Vector 27 Vector 28 Vector 29 Vector 30 Vector 31 Vector 32 Vector 33 Vector 34 Vector 35 Vector 36 Vector 37 Vector 38 Vector 39 (00020H) (00024H) (00028H) (0002CH) (00030H) (00034H) (00038H) (0003CH) (00040H) (00044H) (00048H) (0004CH) (00050H) (00054H) (00058H) (0005CH) (00060H) (00064H) (00068H) (0006CH) (00070H) (00074H) (00078H) (0007CH) (00080H) (00084H) (00088H) (0008CH) (00090H) (00094H) (00098H) (0009CH) : INTWDT : INTP0 : INTP1 : INTP2 : INTP3 : INTP4 : INTP5 : System reserved : INTCM00 : INTCM01 : INTCM10 : INTCM11 : INTCM21 : INTCM31 : INTD0 DMA#0_MAIN : INTD0S DMA#0_SUB : INTD1 DMA#1_MAIN : INTD1S DMA#1_SUB : INTSER0 : INTSER1 : INTSR0/INTCSI0 : INTSR1/INTCSI1 : INTST0 : INTST1 : INTSIT : System reserved : System reserved : System reserved : INTPAI : INTAD : System reserved : System reserved
34
PD70433
Vector 40 Vector 41 Vector 42 Vector 43 Vector 44 Vector 45 Vector 46 Vector 47
(000A0H) (000A4H) (000A8H) (000ACH) (000B0H) (000B4H) (000B8H) (000BCH)
: System reserved : System reserved : System reserved : System reserved : System reserved : System reserved : System reserved : System reserved
When V1 = 0, V0 = 1 : Vector 72 Vector 73
* * *
(00120H) (00124H)
* * *
: INTWDT : INTP0
* * *
Vector 110 Vector 111
(001B8H) (001BCH)
: System reserved : System reserved
When V1 = 1, V0 = 0 : Vector 136 Vector 137
* * *
(00220H) (00224H)
* * *
: INTWDT : INTP0
* * *
Vector 174 Vector 175
(002B8H) (002BCH)
: System reserved : System reserved
When V1 = 1, V0 = 1 : Vector 200 Vector 201
* * *
(00320H) (00324H)
* * *
: INTWDT : INTP0
* * *
Vector 238 Vector 239
(003B8H) (003BCH)
: System reserved : System reserved
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PD70433
3.6 REGISTER FILE SPACE The register file space is shown in Figure 3-5. The size of the register file space is 512 bytes, and a maximum 16-bank register set can be set. The register file space is separate from the memory space, and in addition to accesses using a register manipulation instruction as with the V25 and V35, the register file space can be accessed as data memory by adding a special prefix instruction (IRAM:) to a memory manipulation instruction. (Access is performed asynchronously independently of the external bus cycle. When the IRAM: prefix instruction is added to a memory manipulation instruction, the CPU performs a data access with the low-order 9 bits of the memory address offset value as the register file address. In this case, segment register and physical address addition is not performed, and an external bus cycle is not initiated. Example Label1: MOV MOV IRAM : [0024H], AW ..... <1> ..... <2> [0056H], BW
<1> This shows the case where data is transferred to the register file space using an "IRAM:" prefix instruction. The AW register value is stored in address 24H of the register file. <2> This shows the case where an instruction for data transfer to the memory space is used. If the IRAM prefix instruction is added to the primitive block transfer instruction and BCD operation instruction, which specify the source block and destination block, it becomes effective for the destination block. Also, the macro service conrol word area (008H to 03FH), the macro service work area (000H to 007H), and the area used by the macro service channel (008H to 0FFH) are allocated in overlapping fashion in the file space. If a specific macro service which requires work area (RTOPTRN) is not used, these work areas can be used as data space.
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PD70433
Figure 3-5. Register File Space
000H Macro Service Work Area Macro Service Control Word Area 008H 03FH +02H 1 0 4 0H 2 0 6 0H 3 0 8 0H 4 0A 0H 5 0C 0H 6 0E 0H 7 1 0 0H 8 1 2 0H 9 1 4 0H 10 1 6 0H 11 1 8 0H 12 1A 0H 13 1C 0H 14 1E 0H 15 1FFH +1EH +1CH +1AH +18H BH DW DH CW CH AW AH AL CL DL +16H SP BW BL +14H BP +12H IX +10H IY +0EH DS1 +0CH PS +0AH SS Macro Service Channel Area 0FFH +08H DS0 +04H PSW Save +06H PC Save Vector PC/DS3 + 0 0 H 15 87 DS2 0
0 0 0H Register Bank 0 0 2 0H
(Offset from the starting address of each register bank)
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3.7 I/O SPACE The V55PI has a 64K-byte I/O space. The I/O space map is shown in Figure 3-6. The I/O space is accessed using address bus/data bus and control signals (IORD, IOWR, etc). 0 is output from the unused high-order 8 bits of the address bus. Wait cycles can be inserted in an I/O cycle by software and the READY pin. The area FF80H to FFFFH of the I/O space is a reserved area, in which two V55PI on-chip peripheral DMA input/output read/write pointers (IOP) are allocated. The address of IOP0 is FF94H, and the address of IOP1 is FFB4H. When the CPU executes an input/output instruction with an IOP address as an operand, the DMA controller performs a read/write of data in the DMA controller transfer buffer, with the IOP contents as the address value, and increments (or decrements) the IOP value automatically in accordance with the contents of the DMA control register. Therefore, data written by the DMA controller can be referenced by an input/output instruction, and conversely, data written by an input/output instruction can be transferred by the DMA controller. Figure 3-6. I/O Map (64K Bytes)
0000H
FF80H FF94H FFB4H IOP 0 : IOP 1 : FFFFH
Reserved Area
Remark
IOPn corresponds to the DMA read/write pointer (DPTCn).
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PD70433
4. BUS CONTROL FUNCTIONS
With the V55PI pin, refer to 1.1.2 (1) "Pin function for bus control". As regards pins which have an alternate function as port pins, when that function is used, the corresponding function must be selected by means of the port mode control register (PMCn). 4.1 WAIT FUNCTION
The V55PI divides the basic memory space (000000H to 0FFFFFH) into a maximum of 4 blocks with a variable memory size, divides the uppermost extended memory space area (100000H to FFFFFFH) into two areas with a variable memory size, and performs wait control for each block. The memory size of each block in the basic memory space is specified by the memory block control register (MBC). Figure 4-1 shows the memory block configuration when A9H has been set for the MBC register value. Figure 4-1. Partitioned Memory Control
1 0 1 0 1 1 0 1
MBC MB31 MB30 MB21 MB20 MB11 MB10 MB01 MB00
Main Memory Space 00 Block 0 01 00 10 Block 1 01 00 01 10 Block 3 11 00 01 10 11 11 Block 4 1M Bytes 2M Bytes 4M Bytes 6M Bytes 8M Bytes 10 Block 2 896K Bytes 11 512K Bytes 640K Bytes 768K Bytes 256K Bytes 128K Bytes
Block 5
16M Bytes
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Figure 4-2. Memory Wait Control
7 (BLOCK3) PWC1 DW31 DW30 DW21 DW20 DW11 DW10 DW01 DW00 6 5 (BLOCK2) 4 3 (BLOCK1) 2 1 (BLOCK0) 0
7
6
5
4
3 (BLOCK5) DW51
2
1 (BLOCK4) DW41
0
(BLOCK4) (BLOCK1) PWC0 AW1 AW0
(I/O Space) IOW1 IOW0
DW50
DW40
Data Wait (DW, IOW)
DWn1/IOW1 0 0 1 1 DWn0/IOW0 0 1 0 1 Wait State 0 *1 1 *2 2 *2 3 *2
* 1. 2.
READY signal is ignored. Additional control by means of READY signal is also possible.
Address Wait (AW)
AWn 0 AW0 1 0 AW1 1 Inserted (block 4) Inserted (block 1) Not inserted (block 4) Wait State Not inserted (block 1)
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4.2 REFRESH FUNCTION The following functions are provided to refresh DRAM and pseudo-SRAM. * Function to insert periodically a refresh cycle in a series of bus cycles * Refresh address output function to refresh DRAM and pseudo-SRAM * Function to generate a refresh cycle in hold mode and HALT mode. * Function to insert a wait state in a refresh cycle 4.2.1 Refresh Mode Register (RFM) The RFM register is an 8-bit register to control refresh operation. A refresh cycle can be selected from the time base counter output tap. While a refresh request is held by another bus cycle if the next refresh request is generated, only the latter is valid. The RFM register value after a reset is 77H. 4.2.2 Wait Control in Refresh Cycle A wait state can be inserted in a refresh cycle. The specified number of wait states is inserted for memory block 4 by the programmable wait control register (PWC0) or READY pin. 4.2.3 Refresh Address Bus pins AD0 to AD15 and A16 to A19 are activated in a refresh cycle. For each refresh cycle, the count is performed in one-address increments from x00000 to x1FFFFF in the case of the external 8-bit bus width, and in two-address increments from x00001H to xFFFFF in the case of the external 16-bit bus width (the minimum address is returned to after the maximum address). After initialization by a reset, count-up is started from x00000H in the case of the external 8-bit bus width and x00001H in the case of the external 16-bit bus width. In the case of the external 16-bit bus width, the refresh address minimum address bit (A0) is fixed at "1" and the DEX pin output is also fixed at "1". A20 to A23 are undefined in a refresh cycle.
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5.
INTERRUPT FUNCTIONS
The V55PI incorporates a powerful interrupt controller (INTC) which controls multiple-interrupt servicing for a total of 25
maskable hardware interrupt requests: 19 internal and 6 external. The interrupt controller controls multiple-interrupt servicing based on programmable priority. The following functions are provided as interrupt servicing modes: vectored interrupt function, macro service function, register bank switching function. 5.1 FEATURES
V55PI interrupt functions offer the following features: * Comprehensive servicing states for interrupt requests * Vectored interrupt function : Branch to interrupt service routine specified by vector table * Register bank switching function * Macro service function : High-speed interrupt response by automatic register bank switching : High-speed interrupt servicing by microprogram (firmware)
* 4-level programmable priority order control * Interrupt multiprocessing control according to the priority * Rich variety of macro service functions (following 7 modes) closely tied to V55PI on-chip peripheral hardware EVTCNT : Event count processing
BLKTRS : Data transfer between special function register and external memory buffer BLKTRS-C : Data transfer between special function register and external memory buffer (with transfer data DTACMP DTADIF RTOPTRN detection function) : Special function register status detection : Time measurement by timer capture function : Automatic control of real-time output port
DTACMP-M : Data transfer between external I/O and memory * 7 external interrupt request inputs (NMI, INTP0 to INTP5) * Maskable interrupt requests are individually maskable. A list of interrupt sources is given in Table 5-1.
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Table 5-1. Interrupt Sources (1/2)
Interrupt Classification
Default Priority
Interrupt Request Signal NMI
Interrupt Source
Interrupt Request Control Register
Generating Source NMI pin input
Generating Unit --- WDT
Default Vector Table Number 2 8 9 10 11
Vectored Address
Macro Service
Register Bank Switching No
Macro Service Control Word Address
1 Nonmaskable 2 3 4 5 6 7 8 9 10 Maskable 11 12 13 14 15 16 17 18
00008H 00x20H 00x24H 00x28H 00x2CH 00x30H 00x34H 00x38H 00x40H 00x44H 00x48H 00x4CH 00x50H 00x54H 00x58H 00x5CH 00x60H 00x64H
No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
-- WDT INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTCM00 INTCM01 INTCM10 INTCM11 INTCM21 INTCM31 INTD0 INTD0S INTD1 INTD1S IC9 IC10 IC11 IC12 IC13 IC14 IC16 IC17 IC18 IC19 IC20 IC21 IC22 IC23 IC24 IC25 Watchdog timer overflow INTP0 pin input INTP1 pin input INTP2 pin input External INTP3 pin input INTP4 pininput INTP5 pin input CM00 match detection CM01 match detection CM10 match detection Timer CM11 match detection CM21 match detection CM31 match detection DMA channel 0_main DMA channel 0_sub DMA DMA channel 1_main DMA channel 1_sub 24 25 Yes Yes 19 20 21 22 23 Yes Yes Yes Yes Yes 12 13 14 16 17 18 Yes Yes Yes Yes Yes Yes No Yes Yes Yes
-- 012H 014H 016H 018H 01AH 01CH 020H 022H 024H 026H 028H 02AH 02CH 02EH 030H 032H
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44
Interrupt Classification Default Priority Interrupt Request Signal INTSER0 INTSER1 INTSR0/ 21 INTCSI0 INTSR1/ 22 Maskable 23 24 25 26 27 INTCSI1 INTST0 INTST1 INTSIT INTPAI INTAD IC30 IC31 IC32 IC36 IC37 IC29 IC28
Interrupt Request Control Register
Table 5-1. Interrupt Sources (2/2)
Interrupt Sourse Generating Source UART reception error (ch0) UART reception error (ch1) UART reception (ch0)/ Generating Unit
Default Vector Table Number 26 27
Vectored Address
Macro Service
Register Bank Switching Yes Yes
Macro Service Control Word Address 034H 036H
19 20
IC26 IC27
00x68H 00x6CH
No No
Yes
28 00x70H Yes Serial I/F Yes 29 00x74H Yes 30 31 SIT Parallel I/F
A/D converter
Yes
038H Yes Yes 03AH Yes Yes Yes Yes Yes Yes No No No No No -- No No Yes 03CH 03EH -- -- 008H
Serial transmission/reception (ch0) UART reception (ch1)/ LDMA channel 5 UART transmission (ch0) UART transmission (ch1) STM match detection Parallel I/F A/D converter Divide error BRK flag (single-step) BRK3 instruction BRKV instruction 00x78H 00x7CH 00x80H 00x90H 00x94H 00000H 00004H 0000CH 00010H 00014H 00018H 00x*H -- 0001CH
Yes Yes No Yes Yes No No No No No No No No No
32 36 37 0 1 3 4 5
Software CHKIND instruction -- -- -- Input/output instruction (IBRK flag) BRK imm8 BRKCS instruction FP0 instruction/ Exception trap 7 Exception trap No -- 6 * --
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* Indicates that the value is variable in the range 0 to 255 (0 to FFH). Remarks "x" indicates that the value is determined by the V0 and V1 bits of the IMC register.
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5.2 INTERRUPT RESPONSE METHODS The V55PI has three interrupt response methods: a vectored interrupt function, register bank switching function, and macro service function. In the case of a maskable interrupt request, one of these functions can be selected by means of the interrupt request control register (ICxx) for each interrupt source according to the purpose of the interrupt. The on-chip interrupt controller handles interrupt requests according to the set response method. 5.2.1 Vectored Interrupts A vectored interrupt can only be acknowledged in the interrupt enabled state (EI state). When a vectored interrupt is acknowledged, the CPU enters the interrupt disabled state (DI state), and the current PSW contents and PC and PS contents are saved to the stack. Then the corresponding vector is selected from the vector table, and the interrupt service routine is started at the address indicated by that vector. Vector numbers are fixed for each interrupt source. In the DI state, interrupts are held pending, and are acknowledged when the EI state is set again. The return from the interrupt is performed by an RETI instruction. In the case of a hardware interrupt other than a nonmaskable interrupt, an FINT instruction must be executed before the return instruction. When a return is made from an interrupt, the PC, PS and PSW are restored from the stack. Figure 5-1. Interrupt Acknowledge Operation (Performed in Sequence <1> <4>)
Vector Table
Stack
nx4 SP - 6 nx4+2 SP - 4 SP - 2 n: Vector Number
<4>
<2> SP SP - 6
PC
<1>
PS
PSW IE =0
<3>
BRK = 0
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5.2.2 Register Bank Switching Function In the V55PI, general register sets are mapped onto on-chip RAM, and register sets can be held in up to 16 banks. Interrupt servicing is performed by automatically switching the register bank when a BRKCS or TSKSW instruction is executed or when an interrupt is responded to. Because saving of registers to the stack previously performed by software is not required, high-speed switching of the program execution environment is possible. The register bank switching sequence is performed as follows (See Figure 5-2). <1> The contents of PSW is saved to temporary register. <2> The register bank is switched. <3> IE and BRK are set to 0. <4> The contents of PSW which is saved to the PC and the temporary register are saved to the saving area, respectively. <5> The interrupt service routine start address offset value is loaded from the vector PC area in the register bank to PC. Figure 5-2. Register Bank Switching Sequence (In Case of Register Bank Switching by Interrupt)
Old Register Bank AW CW DW BW SP BP IX IY DS1 PS SS DS0
New Register Bank for Interrupt Servicing AW CW DW BW SP BP IX IY DS1 PS SS DS0
<4>
PC Save PSW Save Vector PC/DS3 DS2 PC PSW PC Save
<4> <5>
PSW Save Vector PC/DS3 DS2
<1>
Temporary Register
<2> Register Bank Switching <3> IE = 0, BRK = 0
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PD70433
5.2.3 Macro Service Function The macro service function performs processing of simple data transfers, etc., by means of a microprogram (CPU internal dedicated firmware) started by generation of an interrupt request. The simple, standardized interrupt servicing which was coded and executed by a user program is performed automatically. Macro service processing is caused by an interrupt request and is performed. Macro service is designed to minimize as far as possible the frequency of generation of interrupts consisting mainly of software processing, hold down the software overhead due to a series of processes used in an interrupt (register saving, initialization, register restoration, return from the interrupt routine), and improve the CPU efficiency. Processing performed by the macro service is transparent in terms of software, and it is possible to process as a single mass of data what was previously processed by software byte by byte, allowing more efficient programming. The V55PI macro service supports not only the simple data transfers used in the V25 and V35, but also various operating modes closely linked to the on-chip V55PI peripheral hardware, as shown below. (a) EVTCNT (EVENT COUNTER) The counter is updated each time the macro service are generated, and when the counter reaches 0 the macro service for the corresponding interrupt source is terminated and a vectored interrupt or a register bank switching is generated. (b) DTACMP (DATA COMPARE) The interrupt source specific SFR and preset byte data are compared, and if they match, the macro service for the corresponding interrupt source is terminated and a vectored interrupt or register bank switching is generated. (c) DTADIF (DATA DIFFERENCE) The difference in using the timer/counter unit capture register is calculated. This is initiated by a timer interrupt: the value of the capture register latched last time is subtracted from the value of the capture register latched this time, and the result is stored in the previously specified memory buffer. When processing has been performed the previously set number of times, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (d) BLKTRS (BLOCK TRANSFER) A data transfer is performed between the previously specified memory buffer and SFR. When the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (e) BLKTRS-C (BLOCK TRANSFER WITH CHARACTER SEARCH) A data transfer is performed between the previously specified memory buffer and SFR. When the previously set number of data transfers have been completed, or when the transfer data matches the previously set character data, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated. (f) RTOPRTN (RTOP TRANSFER) Data to be output to the real-time output port is transferred to the port 7 buffer (P7H, P7L), and data which specifies interval for output to the real-time output port is transferred to the timer compare register (CM00, CM01). (g) DTACMP-M (DATA COMPARE WITH CHARACTER MASK) The logical product of the status data read from the external I/O and the previously set mask data is performed. The previously set byte data is compared with the result. If it matches, a data transfer is performed between the external I/ O and memory. If it does not match, or if the previously set number of data transfers have been performed, the corresponding interrupt source macro service is terminated, and a vectored interrupt or register bank switching is generated.
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PD70433
6. DMA FUNCTION (DMA CONTROLLER)
The V55PI incorporates a 2-channel DMA controller which controls execution of memory-to-I/O or memory-to-memory DMA transfers on the basis of DMA requests generated by an on-chip peripheral hardware (serial interface, parallel interface, or timer), the external DMARQ pin or a software trigger. Each channel of the DMA controller further comprises a main channel and a sub-channel: the operating mode determines whether the main channel and sub-channel are used as a single channel or as separate channels. When used as separate channels, function for a maximum of 4 channels can be constructed. 6.1 FEATURES * Two independent DMA channels (max. 4-channel configuration possible) * Four transfer modes * Single transfer mode ... One DMA transfer cycle is executed in response to one DMA request.
* Demand release mode ... Consecutive DMA transfer cycles are executed while DMA request is active. * Single-step mode ... DMA transfer cycles and CPU bus cycles are executed alternately after DMA * Burst mode * Five operating modes * Intelligent DMA mode-1 (ring buffer system) ... DMA transfers to ring buffer are controlled. * Intelligent DMA mode-2 (counter control system) ... Transfer data is transferred consecutively, divided into * Next address specification mode * 2-channel operating mode * Memory-to-memory transfer mode * 3 clocks/1 bus cycle (no wait case) * Transfer objects * External I/O memory ... 1 DMA transfer cycle/1 bus cycle an arbitrary number of bytes. ... Consecutive transfers are possible between different transfer buffers. ... Main channel and subchannel are used as independent channels. ... Two bus cycles are started for one DMA transfer cycle, and memory-to-memory transfer is executed. request generation. ... For each DMA request, the specified number of DMA transfer cycles are executed consecutively.
* SFR (internal I/O) memory ... 1 DMA transfer cycle/1 bus cycle * Memory memory (memory includes SFR) ... 1 DMA transfer cycle/2 bus cycles * Byte transfer/word transfer selectable * Transfer address increment/decrement/non-update selectable * DMA transfer end signal (TCE0, TCE1) output * 24-bit DMA memory address registers (MAR0, MAR1) * 21-bit terminal counters (TC0, TC1) * External DMA request signal input pins (DMARQ0, DMARQ1: alternate function as port P80 and P81 pins) * External DMA acknowledge signal output pins (DMAAK0, DMAAK1)
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PD70433
Table 6-1. Transfer Modes
DMA Start Source Transfer Mode On-Chip Peripheral Single transfer mode Demand release mode Software Trigger Reset of EDMA bit of DMAMn register Stops when the DMARQ pin is driven low during the transfer. Reset of EDMA bit of DMAMn register DMARQ Pin STOP Method Interrupt
Available
Available
Available
Acknowledged
Not Available
Not Available
Available
Not acknowledged during transfer. Acknowledged at other times. Acknowledged register
Single step mode Burst mode
Available*
Available
Available
Reset of EDMA bit of DMAMn
Available*
Available
Available
None (stop disabled during the transfer)
Not acknowledged
*
The DMA start source is an on-chip timer interrupt, and transfer is possible only when the transfer I/O specification is external. Table 6-2. Correspondence Between Operating Modes and Transfer Modes
Possible Transfer Modes* Operating Mode Transfer Type <1> Intelligent DMA mode-1 (ring buffer method) Intelligent DMA mode-2 (counter control method) Next address specification mode 2-channel operating mode (Stop at end) (Repetition) (Stop at end) (Repetition) I/O (SFR) Memory Memory I/O (SFR) I/O (SFR) Memory I/O Memory I/O Memory Memory Memory Memory Memory Yes <2> Yes <3> No <4> No
No Yes Yes Yes Yes Yes
No Yes Yes Yes No No
Yes No Yes Yes Yes Yes
Yes No Yes No Yes No
Memory-memory transfer mode
*
Transfer modes <1> Single transfer mode <2> Demand release mode <3> Single step mode <4> Burst mode
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PD70433
7. SERIAL INTERFACE FUNCTIONS
The V55PI is equipped with a 2-channel serial interface unit (ch0, ch1). The two communication protocols supported by the V55PI are as follows: (1) (2) Asynchronous Clocked UART CSI
SBI: IOE:
2-wire serial bus interface I/O expansion 3-wire serial interface
7.1 FEATURES * Two communication protocols supported * Two serial channels * Wake-up function * On-chip dedicated baud rate generator * DMA request generated by completion of transmission/reception (transmit/receive data DMA transfer is capable) 7.2 PROTOCOLS The UART is an asynchronous serial interface which achieves data synchronization by means of start/stop bits, and is functionally enhanced UART functions compared with previous single-chip microcontroller. The CSI (clocked serial interface) is a clocked serial interface which achieves synchronization by transmission/reception of a clock. The CSI is a subset of the standard serial bus interface specification for NEC single-chip microcontrollers, and I2C functions are not supported. The wake-up release function is implemented by using macro service. Table 7-1. Supported Protocols
Supported Protocols Serial Interface Unit Clocked (CSI) SBI Channel 0 Channel 1 Yes No IOE Yes Yes Asynchronous (UART) Yes Yes
The UART function or CSI function can be programmably selected for each channel. Protocol selection is performed by means of the protocol selection register (ASP).
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PD70433
7.3 7.3.1
UART Features 95 to 390 Kbps (with 12.5 MHz system clock ) 123 to 500 Kbps (with 16 MHz system clock )
* Transfer rate:
* Full-duplex operation capability * On-chip dedicated (transmission and reception) baud rate generators * Wake-up function * Zero parity function * Parity error detection * Framing error detection * Overrun error detection * Three dedicated UART interrupt sources * UART receive error interrupts (INTSER0, INTSER1) * UART reception interrupts (INTSR0, INTSR1) * UART transmisstion interrupts (INTST0, INTST1) * Macro service function * UART reception interrupts (INTSR0, INTSR1) * UART transmission interrupts (INTST0, INTST1) Figure 7-1. UART Block Diagram
INTSRn
RxB
TxB
INTSTn UARTM
RxDn
Shift Register
UARTS
AS
Shift Register
TxDn
Reception Control Parity Check
ERP ERF ERO INTSERn
Transmission Control Parity Addition
CTS
Transmit Serial Clock
TxC*
External Clock Control
Receive Serial Clock
*
Channel 0 only
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7.4
CLOCKED SERIAL INTERFACE (CSI)
7.4.1 Features * Transfer speed: Max. 3.125 Mbps (with 12.5 MHz system clock ) Max. 4.0 Mbps (with 16 MHz system clock ) * Half-duplex communication * Data length: 8-bit unit * External/internal clock selection function * Data MSB-first/LSB-first selection function * SBI mode (2-wire NEC type serial bus) ... ch0 only * Address/command/data identification function * Function for chip selection by address * Wake-up function * Acknowledge signal (ACK) control function * Busy signal (BUSY) control function The V55PI clocked serial interface has the following two operating modes. (1) 3-wire serial I/O mode (IOE mode) In this mode, 8-bit data transfer is performed using three lines: the serial clock (SCK), and serial data input and output (SI, SO). This mode is useful when connecting an I/O device, display controller, etc., which incorporates a conventional clocked serial interface. The functions of the V25 and V25+TM have been enhanced, and data MSB-first/LSB-first selection is possible. (2) Serial bus interface mode (SBI mode) In the SBI mode, communication is performed with multiple devices by means of two lines: the serial clock (SCK)
and the serial bus interface (SB0 or SB1). This mode conforms to the NEC serial bus format. In the SBI mode, the sender can output to the serial data bus an address to select the target device for serial communication, a command which gives a directive to the target device, and actual data. Thus there is no need for the line for handshaking required when multiple devices are connected with a conventional clocked serial interface, allowing input/output ports to be used efficiently. In addition, wake-up release is performed using macro service.
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PD70433
8. PARALLEL INTERFACE FUNCTIONS
The V55PI incorporates a parallel interface unit for data input on a Centronics specification interface, and general data input/output. 8.1 FEATURES The following features are provided as parallel interface functions: * Centronics specification interface compatibility * Input/output mode switchable by software * BUSY signal manipulable by software * BUSY signal and ACK signal output timing settable * Initialization by external interrupt * Dedicated parallel interface interrupt source * Parallel interface interrupt (INTPAI) * DMA request signal generation in parallel transmission/reception * INTPAI functions as a DMA start trigger. * Signal pin input/output characteristic is TTL level (Centronics specification interface)
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PD70433
Figure 8-1. Parallel Interface Block Diagram (a) Input mode
Input Data Latch OE DATASTB IBF S R
Internal Bus
PD0-PD7
Q
MB0, 1
BUSY Control Circuit
BUSY
DATA RD
DMA Request
ACK Control Circuit
ACK
PAI Timer Counter ACK Timing Control
RESET
IBSY S R
INTP5
(b)
Output mode
Output Data Latch DATA WR WR
PD0-PD7
Internal Bus
PAI Timer DATASTB Counter
DMA Request INTPAI Request
INT/ DMA Request Control
BUSY
ACK
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9. TIMER FUNCTION
The V55PI timer unit can be used as an interval timer, free-running timer and event counter. It is also possible to manipulate P7 as a real-time output port, synchronized with interrupt requests generated by the timer. The normal timer function and real-time output port function are described here. 9.1 FEATURES
The timer function offers the following features. * 16-bit timer x 4 * Two count clock sources are selectable * System clock scaled output selectable (/8, /32: system clock ) * External input pulses from TI pin * External count output signal (TOn output) * Three 16-bit capture registers on chip (external interrupt input signals INTP0 to INTP2 as triggers) * Six dedicated timer unit interrupt source (INTCM00, INTCM01, INTCM10, INTCM11, INTCM21, INTCM31) * Real-time output port function synchronized with timer interrupts 9.2 TIMER UNIT CONFIGURATION The timer unit configuration is shown in Figure 9-1, and the function of each timer in Table 9-1. Table 9-1. Timer Functions
Timer 0 Count function Capture function Compare function Function Timer output function Toggle output Set/reset output Available Available Available Available
Timer 1 Available Available Available Not Available
Timer 2 Available Not Available Available Available
Timer 3 Available Not Available Available Not Available
Not Available Not Available
Not Available Not Available
Available Available
Available
Cascading
55
56
Timer 0 /8
16-Bit Free Running Timer (TM0)
Figure 9-1. Timer Unit Block Diagram
Timer 1 OVF TI /8 INTP2
16-Bit Timer Register/Event Counter 1 (TM1)
OVF Clear
INTP0 INTP1
Capture Register (CT00) Capture Register (CT01) Compare Register (CM00) Compare Register (CM01) INTCM00 INTCM01 T T
Capture Register (CT10) Compare Register (CM10) Compare Register (CM11) INTCM10 INTCM11
TO00 TO01 To Real-Time Output Port
Timer 2 /8 /32 Clear
16-Bit Timer Register 2 (TM2)
Timer 3 INTCM21 /8 /32
16-Bit Timer Register 3 (TM3)
Clear Clear, Count Enable
INTCM31
Compare Register (CM20) Compare Register (CM21) Compare Register (CM22) Compare Register (CM23)
S R S R T
Q
TO20
Compare Register (CM30) Compare Register (CM31)
S R
Q
TO30
Q TO21
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To DMA Controller
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9.3 REAL-TIME OUTPUT PORT FUNCTION Port 7 of the V55PI incorporates a real-time output port function, and can output the contents of the port 7 buffer (P7H, P7L) at programmable intervals from timer 0 bit-wise. 9.3.1 Real-Time Output Port Configuration The real-time output port configuration is shown in Figure 9-2. It comprises the following buffer registers, output and control registers. (1) Port 7 buffer (P7H, P7L) The buffer registers hold the data to be output next when port 7 is set to the real-time output port mode. The port 7 buffer contents are not affected by reset input. (2) Real-time output port (RTP) Real-time output port output data is held in this port after being taken from the port 7 buffer, and output from the
pins. RTP can be read or written to by an 8-bit or single-bit manipulation instruction (unlike the port 7 output port). (3) Real-time output port delay specification regiser (RTPD) and delay counter
This register is set and used when using the mode in which a delay time is inserted in the timing for output from the real-time output port (RTP) to the output pins. If the P7L bit is set to "0", "0" is output to the corresponding output pin bit after the elapse of the delay time equivalent to the count clock cycle time set in the real-time output port delay specification register after the time at which the transfer trigger is generated. The delay time in this case is counted by the delay counter. (4) Real-time output port control register (RTPC) RTPC specifies the operating mode of the real-time output port. It is possible to specify whether or not a delay is
to be inserted when data is output, the timing for transferring data to the port 7 buffer, the transfer timing trigger, and so on.
57
Output Latch RTP Bit 3
Selector
S R
Q
58
To Port 7 P77 P76
Figure 9-2. Real-Time Output Port Operation
RTPC Real-Time Output Port Control Register 8 Internal Bus
TRG, BYTE DLY
P7H Port 7 Buffer
P7L Port 7 Buffer INTCM00 (Timer 0) INTCM01 (Timer 1)
Borrow Delay Counter Preset RTPD Delay
Delay Specification Register
/2
No Delay Output Latches RTP7 to RTP4
P75
P74
P73
P72
P71
P70
Control Output Signals
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9.3.2 Real-Time Output Port Operation Real-time output port specification is performed bit-wise by the port 7 mode control register (PCM7). Port 7 (P7), the port 7 buffer (P7H, P7L) and the real-time output port can be accessed as real-time output ports. Data output is performed as described below. When output data is written in the port 7 buffer (P7H, P7L), the port 7 buffer contents are transferred to the real-time output port (RTP) and output to the pins in synchronization with the timing of an interrupt request from timer 0 (INTCM00, INTCM01), or a write to the TRG bit in the control register (RTPC). An example of the direct control of the output pattern for a real-time output port and the output interval is shown in Figure 9-3. Update data is transferred from the two data storage areas set beforehand in the external memory space to the realtime output function buffer registers (P7H, P7L) and compare registers (CM00, CM01). Figure 9-3. Real-Time Output Port Stepping Motor Control
Register File Space
External Memory Space
Output Data Pointer Buffer Register Address
Compare Register Address
+1 D1 Output Data Area D2 D3 D4 T1 Output Timing Data Area T2 T3 T4 Mode Register Channel Pointer Macro Service Control Word
Output Timing Data Pointer
RC Initial Value
Real-Time Output Counter (RC)
-1 -1
Macro Service Counter
Transfer or Addition
Transfer
Internal Bus Real-Time Output Port
Timer 0
Macro Service Processing
Buffer Register P7H, P7L RTP
Output Latch
Compare Register CM00 or CM01 Interrupt Request Match Free Running Timer TM0
INTCM00 or INTCM01
Real-Time Output Trigger/ Macro Service Activation
fCLK/8
Stepping Motor
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In particular, it is possible to insert a delay time in the timing for output by setting the real-time output port delay specification register (RTPD) pins. If the P7L bit is changed from "1" to "0", it is possible to perform output after inserting a delay time of 2 x the system clock set in the RTPD from the timing at which the transfer trigger is generated. In this case, "0" is output from the corresponding output pin. This delay is counted by the delay counter.
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10. PWM UNIT
The V55PI is provided with an 8-bit precision PWM (pulse width modulation) signal output function. PWM output can be used as a digital-to-analog conversion output by connecting a low-pass filter, etc., externally. This is ideal for the actuator control signal for motors, etc. 10.1 FEATURES The PWM unit offers the following features: * PWM output pulse active level selectable * Frequency: 25 MHz (with 12.5 MHz system clock ) PWM cycle: 40.96 s : 32 MHz (with 16 MHz system clock ) PWM cycle: 32.00 s * Output pulse width (duty): 0, 1/256, ....., 255/256 Resolution: 160 ns (with 12.5 MHz system clock ) 125 ns (with 16 MHz system clock ) 10.2 PWM UNIT CONFIGURATION The configuration of the PWM unit is shown in Figure 10-1. The PWM unit consists of the PWM register (PWM) and PWM control register (PWMC), and an 8-bit counter. The PWM register controls the pulse width (duty) in the PWM output mode. The 8-bit counter is set to 00H by reset input. The PWM register is not affected by reset input.
61
62
8-Bit Counter Comparator PWM Slave Latch PWM Register
Figure 10-1. PWM Unit Block Diagram
Overflow S R Match Detection Signal Q Q Active Level Control PWM Output
Preset 0 0 0 0 0 0 CE ALV PWM Control Register
Internal Bus
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11. WATCHDOG TIMER FUNCTION
The watchdog timer is a function for preventing inadvertent program looping and deadlocks. 11.1 FEATURES * * Three overflow times settable (8.1, 32.7, 131.0 [ms]: system clock = 16 MHz) (10.4, 41.9, 167.7 [ms]: system clock = 12.5 MHz) Output pin provided (WDTOUT pin) which can be directly connected to the RESET pin
11.2 WATCHDOG TIMER CONFIGURATION AND OPERATION Non-generation of a watchdog timer interrupt enables normal operation of the program or system to be confirmed. To use the watchdog function, an instruction (RSTWDT) to clear the watchdog timer (start the count) must be included in at fixed intervals in the program execution time, at the start of a subroutine, etc. If the instruction which clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a watchdog timer interrupt (INTWDT) is generated and the low-level signal is output to the WDTOUT pin to report a program error. The watchdog timer configuration is shown in Figure 11-1. Figure 11-1. Watchdog Timer Configuration Diagram
*1
Frequency Divider
/2 9 /2 11 /2 13
Watchdog Timer (8 bits)
Overflow
WDTOUT Active Timer (5 bits) Clear INTWDT
OVF S R Q WDTOUT
WDTCLR *2 RESET STOP
Oscillation Stabilizing Time Control Circuit
* 1. : System clock 2. WDTCLR: Watchdog timer clearance by instruction
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12. A/D CONVERTER FUNCTION
The V55PI incorporates a high-speed, high-precision 8-bit analog/digital (A/D) converter with four analog inputs (ANI0 to ANI3). The A/D converter uses the successive approximation method, and is provided with four A/D conversion result registers (ADCR0 to ADCR3) which hold the conversion results. 12.1 FEATURES The A/D converter offers the following features: * Incorporates four 8-bit A/D conversion result registers. * Four analog input pins (ANI0 to ANI3) * Two A/D converter conversion operating modes * Scan mode : Performs conversion by selecting multiple analog inputs in sequence. * Select mode : Performs continuous conversion with only one pin used as the analog input. * Two conversion start methods * Hardware start : Started by trigger input (INTP4) * Software start : Started by A/D converter mode register (ADM) bit setting * Generation of conversion end interrupt request (INTAD)
64
Figure 12-1. A/D Converter Block Diagram
Series Resistance String R/2 ANI0 ANI1 ANI2 ANI3 Input Circuit Sample & Hold Circuit R AVREF
Tap Decoder
R/2 AVSS P15/INTP4 External Trigger Comparator AVDD
A/D Converter Mode Register (ADM) 8 Internal Bus
Successive Approxi8 mation Register (SAR)
8
Control A/D Conversion Result Register 0 (ADCR0) A/D Conversion Result Register 1 (ADCR1) A/D Conversion Result Register 2 (ADCR2) A/D Conversion Result Register 3 (ADCR3) INTAD
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Internal Bus
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13. STANDBY FUNCTIONS
The V55PI has two methods for controlling the operating clock as standby functions designed to reduce power dissipation. Transition to either of these standby modes is possible by means of a dedicated instruction. Table 13-1. HALT/STOP Mode Operating Status
Parameter Clock generator Internal system clock 16-bit timer Watchdog timer Hold circuit Operating Stopped
HALT Mode
STOP Mode
Stopped Serial interface Operating Parallel interface A/D Converter Interrupt request controller DMA controller IORD, IOWR AD0 to AD15 Bus lines A16 to A23 R/W output Refresh operation Data retention High level Change accordng to DMAC operating status High level Operating All internal data retained (CPU status, RAM contents, etc.) * * * * NMI INTWDT Maskable interrupt request RESET input High level
Retained
High level Stopped All internal data retained (CPU status, RAM contents, etc.)
Release method
* NMI * RESET input
13.1 HALT MODE In this mode, the CPU operating clock is halted. Setting the CPU idle time to the HALT mode enables overall system power dissipation to be reduced. The HALT mode is entered by executing the HALT instruction. In the HALT mode the CPU clock and program execution are stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1. When the HALT instruction is executed during a DMA transfer, transition to the HALT mode is deferred until the transfer bus cycle for one DMA request is completed.
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13.2 STOP MODE In this mode, clock oscillation is stopped. This is effective when the entire application system is stopped, and offers extremely low power dissipation. The STOP mode is entered by executing the STOP instruction. In this mode all clocks are stopped. Program execution is stopped, and all register and on-chip RAM contents immediately prior to the stoppage are retained. The status of each hardware unit is shown in Table 13-1. When the STOP instruction is executed during a DMA transfer, transition to the STOP mode is deferred until the transfer bus cycle for one DMA request is completed. If there is contention between a refresh cycle and STOP instruction execution, transition to the STOP mode is deferred until the refresh cycle is completed.
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14. CLOCK GENERATOR
The clock generator supplies various clocks to the CPU and peripheral hardware, and controls the CPU operating mode. 14.1 CLOCK GENERATOR CONFIGURATION AND OPERATION The clock generator is configured as shown in Figure 14-1. The clock generator clock is generated by a crystal resonator or ceramic resonator connected to the X1 and X2 pins. The clock generator output is subjected to waveform shaping (dividing frequency by 2) and selection of the scaling factor by means of the processor control register (PRC), and is then used as the system clock . The system clock scaling factor is specified by the PCK1 and PCK0 bits of the PRC register, and can be selected as 1/2, 1/4, 1/8 or 1/16 the oscillator frequency (fXX). Selecting a low-speed system clock reduces the current consumption of internal circuit, allowing extended operation of a battery-driven system even when the voltage drops. An external clock can be input. In this case, the clock signal should be input to the X1 pin, and leave the X2 pin open. Figure 14-1. Clock Generator
X1 Clock Oscillator X2
Waveform Shaping Frequency Dividers f
XX
1 16 fXX
1/2
1/2
1/2
1/2
1 8 1 4 1 2
fXX fXX fXX
Selector
(=f X )
Time Base Counter
Software Interval Timer Refresh Cycle Generator PWM Baud Rate Generator
PRC PCK0 8 PCK1 TB0 TB1 0 ENCLK 1 1 System Clock CLKOUT Watchdog Timer
fXX
: Oscillator frequency : System clock PRC : Processor control register
68
Internal Bus
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In the V55PI, the frequency divider (time base counter: TBC) which divides the internal system clock is shared by each timer unit. The TBC cannot be read or written to by an instruction. The TBC tap output (divide-by-2n clock) is supplied to the units shown below as a count clock. (1) (2) (3) (4) Refresh cycle generator Software interval timer PWM unit Baud rate generator
The TBC is cleared to 00H only by reset input, after which it is constantly incremented. TBC operation is stopped in the STOP mode. The configuration of the TBC is shown in Figure 14-2. Figure 14-2. Frequency Divider (Time Base Counter, TBC) Configuration
/2 to /2 9 /2 to /2 8
TBC
/2 3 to /2 9 /2 2 and /2 7
PWM
Baud Rate Generator
Refresh Cycle Generator
Software Interval Timer
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15. SOFTWARE INTERVAL TIMER FUNCTION
The V55PI incorporates a 16-bit software interval timer as a timer for software timer functions and watch functions. 15.1 SOFTWARE INTERVAL TIMER CONFIGURATION The configuration of the software interval timer is shown in Figure 15-1. Figure 15-1. Software Interval Timer Configuration
/4 /128
Software Timer Counter (STC)
Clear
Software Timer Counter Compare Register (STMC) Match Detection
INTSIT
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16. CODEC INSTRUCTIONS
The V55PI has 9 codec instructions. Using these special instructions on the V55PI enables not only image information MH encoding but also MR encoding which previously required the use of a special device such as an ACEE (advanced compression/expansion engine) to be implemented by means of a small-scale, high-speed codec. 16.1 FEATURES The V55PI has the following 9 codec instructions (4 for compression, 5 for expansion): * Compression instructions (1) Change point table creation instruction: COLTRP (2) Data transmission instruction (transmission of EOL *1, FILL, RTC *2, etc.): ALBIT (3) MH encoding instruction: MHENC (4) MR encoding instruction: MRENC * Expansion instructions (5) EOL detection instruction: SCHEOL (6) 1-bit (tag) detection instruction: GETBIT (7) MH decoding change point table creation instruction: MHDEC (8) MR decoding change point table creation instruction: MRDEC (9) Pixel data creation instruction: CNVTRP MH/MR encoding and MH/MR decoding using these instructions are performed as shown in Figures 16-1 and 16-2. * 1. 2. Note EOL: End Of Line RTC: Return To Control When compression/expansion processing is performed using the V55PI codec instructions, the following should be specified as preconditions. * Compression/expansion is to be performed line by line. * Consideration must be given to task switching and interrupt generation during compression processing. * The number of bits processed per line must not be changed during processing of one page. * The segment value must be changed for data over 64 Kbytes that straddles segments during processing.
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Figure 16-1. MH/MR Encoding Processing Flow
Start
K=0 L = Number of lines
K=0
No
Yes
Data transmission instruction (EOL + tag bit "1" transmission) Data transmission instruction (EOL + tag bit "0" transmission)
Change point table creation instruction
Change point table creation instruction
MH encoding instruction
MR encoding instruction
K = K factor - 1
K=K-1
Data transmission instruction (FILL transmission)
L=L-1
No
L=0 Yes Data transmission instruction (RTC transmission)
End
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Figure 16-2. MH and MR Decoding Processing Flow
Start
EOL detection instruction
Error detection No 1-bit detection instruction (tag bit detection)
Yes
To Error Processing
Tag = 1 Yes MH decoding instruction
No
MR decoding instruction
* Yes EOL detection at start No Yes End Error detection No Pixel data creation instruction To Error Processing Yes Error detection No Pixel data creation instruction End EOL detection at start No Yes
*
RTC is detected by two EOLs.
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16.2 MEMORY MAP The data memory areas required by the V55PI's codec instructions are shown below. (1) Register file space This is the register bank for parameter setting. (2) User RAM Encoding line change point table : Storage area for change point information required for performing encoding Reference line table Image data buffer Transmit/receive buffer Print buffer (3) User ROM Encoding conversion table : Conversion table for MH/MR encoding Decoding conversion table : Conversion table for MH/MR decoding (4) Access to Expanded Memory Space The 16-Mbyte expanded memory space can be accessed by using the expanded segment override prefix instruction (DS2: or DS3:). However, the segment registers DS2 and DS3 that are used during instruction execution are DS2 and DS3 in the parameter setting register banks of each instruction. Table 16-1. Instructions to which Expanded Segment Override Prefix Can Be Attached In the case of n bit/lines, a maximum area of 2n + 4 bytes is required. : Reference line change point information storage area : Storage area for pixel data read from scanner in encoding, or encoding data received from modem in decoding : Buffer for transferring encoded data to modem/scanner : Buffer for transferring decoded pixel data to recording system
DS2: Yes Yes Yes Yes Yes Yes Yes Yes Example
DS3: Yes No Yes No Yes No No Yes
CODEC Instruction COLTRP MHENC MHDEC MRENC MRDEC SCHEOL GETBIT CNVTRP
DS2 : DS3 : COLTRP DS2 : SCHEOL The relationship between encoding instructions and data in memory is shown in Figure 16-3, and the relationship between decoding instruction and data in memory is shown in Figure 16-4.
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Figure 16-3. Encoding Instructions and Data in Memory
DMA
Register File
Software
User RAM
Parameter Frame
Data Output Instruction Change Point Table Creation Instruction MH/MR Encoding Instruction
Image Data (1 Line)
Work (Change Points)
User ROM Encoding Conversion Table (512 Bytes) *
Coding Data (1 Line)
*
In case of MH/MR encoding instructions Figure 16-4. Decoding Instruction and Data in Memory
DMA
Register File
Software
User RAM
Parameter Frame
EOL Detection Instruction 1-Bit Detection Instruction MH/MR Decoding Instruction Image Data Creation Instruction
Coding Data
Work (Change Points)
User ROM Decoding Conversion Table (2304 Bytes)*
Image Data (1 Line)
*
In case of MH/MR decoding instructions
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16.3 PROCESSING FLOW The instructions shown in 16.1 "Features" are used in the order shown in Figures 16-5 and 16-6 in encoding/decoding procesing. Figure 16-5. Processing Flow for Encoding of One Line
Start
Data transmission instruction (ALBIT) Transmission of EOL and tag (Pixel Data)
.....
Change point table creation instruction (COLTRP) Change point information for 1 line created, and stored in prescribed storage area (change point table)
Input
Output (Change Point Table) Black Black Black Black White White White White 0 2 1 1 3 1 1 6
.....
1 Word Input MH/MR encoding instruction (MHENC/MRENC) MH/MR encoding for 1 line
Encoded Data Transmision Buffer
Fill transmission
End
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Figure 16-6. Processing Flow for Decoding of One Line
Start
EOL detection instruction (SCHEOL) EOL (000000000001) is detected
1 bit detection instruction (GETBIT) Tag (1 bit) is detected Encoded Data Printer Buffer MH/MR decoding instruction (MHDEC/MRDEC) MH/MR decoding change point information for 1 line is generated and stored in specified area (change point table) Input
Output
(Change Point Table) Black Black Black Black White White White White 0 2 1 1 3 1 1 6
.....
1 Word Input
Pixel data creation instruction (CNVTRP) Pixel data for 1 line is created
Output (Pixel Data) End
.....
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17. INSTRUCTION SET
The V55PI instruction set is upward compatible with the V20/V30 (native mode) and V25/V35 instruction sets. 17.1 INSTRUCTIONS NEWLY ADDED TO V20/V30 AND V25/V35 Instructions which have been added to the V20/V30 and V25/V35 instruction sets, and instructions whose application range has been extended, are shown below. (1) Instructions added to V20/V30.
Mnemonic BRKCS TSKSW MOVSPA MOVSPB BTCLR RETRBI FINT STOP reg 16 Register bank switching instruction reg 16 None Data transfer instruction reg 16 sfr, imm3, short-label None Interrupt instruction None None CPU control instruction Conditional branch instruction Operand Instruction Group
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(2) Instructions added to V25/V35.
Mnemonic IRAM DS2 DS3 None None Extended segment override prefix instruction None DS2, reg16, mem32 DS3, reg16, mem32 xsreg, reg16 MOV xsreg, mem16 reg16, xsreg mem16, xsreg DS2 PUSH DS3/VPC Stack manipulation instruction DS2 POP RSTWDT BTCLRL DS3/VPC imm8, imm8' sfrl, imm3, short-label reg8 mem8 BSCH Bit manipulation instruction reg16 mem16 QHOUT QOUT QTIN ALBIT COLTRP MHENC MRENC SCHEOL GETBIT MHDEC MRDEC CNVTRP imm16 imm16 imm16 None None None None None None None None None Dedicated FAX instruction Queue manipulation instruction Watchdog timer manipulation instruction Conditional branch instruction Data transfer instruction Operand Instruction Group Register file space access override prefix instrution
Remark
VPC: Vector PC
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17.2 INSTRUCTION SET OPERATIONS Table 17-1. Operand Type Legend
Identifier reg, reg' reg8, reg8' reg16, reg16' mem mem8 mem16 mem32 sfr sfrl dmem imm imm3 imm4 imm8 imm8' imm16 acc sreg xsreg src-table src-block dst-block src-string dst-string near-proc far-proc near-label short-label far-label regptr16 memptr16 memptr32 pop-value fp-op repeat IRAM : R () or, /
Description 8/16-bit general register (Destination register in an instruction using two 8/16-bit general registers) Source register in an instruction using two 8/16-bit general registers 8-bit general register (Destination register in an instruction using two 8-bit general registers) Source register in an instruction using two 8-bit general registers 16-bit general register (Destination register in an instruction using two 16-bit general registers) Source register in an instruction using two 16-bit general registers 8/16-bit memory address 8-bit memory address 16-bit memory address 32-bit memory address Special function register location: FFF00H to FFFEFH Special function register location: FFE00H to FFEFFH 16-bit direct memory address 8/16-bit immediate data 3-bit immediate data 4-bit immediate data 8-bit immediate data 8-bit immediate date (1's compliment of imm8) 16-bit immediate data Accumulator AW or AL Segment register Extended segment register Name of 256-byte conversion table Name of source block addressed by register IX Name of destination block addressed by register IY Name of source string addressed by register IX Name of destination string addressed by register IY Procedure start address in current program segment Procedure start address in a different program segment Absolute address in current program segment Relative address of memory in range -128 to +127 bytes from end of instruction Absolute address in a different program segment 16-bit general register holding call address offset in current program segment 16-bit memory address holding call address offset in current program segment 32-bit memory address holding call address offset and segment data in a different program segment Number of bytes removed from stack (0 to 64K, normally an even number) Immediate value which identifies external floating point operation coprocessor operation code Repeat prefix instruction Register file space access override prefix instruction Register set (AW, BW, CW, DW, SP, BP, IX, IY) Omissible Or
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Table 17-2. Operation Code Legend
Identifier W reg, reg' mod, mem (disp-low) (disp-high) disp-low disp-high imm3 imm4 imm8 imm8' imm16-low imm16-high addr-low addr-high sreg xsreg s offset-low offset-high seg-low seg-high pop-value-low pop-value-high disp8 X XXX YYY ZZZ
Description Word/byte specification bit (1: word, 0: byte). However, when s = 1, sign extension byte data is specified as 16-bit operand even if W = 1. 8/16-bit general register specification bits (000 to 111) Memory addressing specification bits (mod: 00 to 10, mem: 000 to 111) Optional 16-bit displacement low byte Optional 16-bit displacement high byte 16-bit displacement low byte for PC relative addition 16-bit displacement high byte for PC relative addition 3-bit immediate data 4-bit immediate data 8-bit immediate data 8-bit immediate data (1's complement of imm8) 16-bit immediate data low byte 16-bit immediate data high byte 16-bit direct address low byte 16-bit direct address high byte Segment register specification bits (00 to 11) Extended segment register specification bits (10 to 11) Sign extension specification bit (1: sign extension, 0: no sign extension) Low byte of 16-bit offset data to be loaded in PC High byte of 16-bit offset data to be loaded in PC Low byte of 16-bit segment data to be loaded in PS High byte of 16-bit segment data to be loaded in PS Low byte of 16-bit data which specifies number of bytes to be removed from stack High byte of 16-bit data which specifies number of bytes to be removed from stack 8-bit displacement for relative addition to PC
Operation code of an external floating point operation coprocessor
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Table 17-3. Operation Description Legend
Identifier AW AH AL BW CW CL DW SP BP PC PSW IX IY PS DS3 DS2 DS1 DS0 SS AC CY P S Z IE V IBRK BRK RB0 RB1 RB2 RB3 VPC (...) disp temp ext-disp8 seg offset + - x / % V xxH xxxxH /
Description Accumulator (16 bits) Accumulator (high byte) Accumulator (low byte) Register BW (16 bits) Register CW (16 bits) Register CL (low byte) Register DW Stack pointer (16 bits) Base Pointer (16 bits) Program counter (16 bits) Program status word (16 bits) Index register (source) (16 bits) Index register (destination) (16 bits) Program segment register (16 bits) Extended data segment 3 register (16 bits) Extended data segment 2 register (16 bits) Data segment 1 register (16 bits) Data segment 0 register (16 bits) Stack segment register (16 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Direction flag Interrupt enable flag Overflow flag I/O break flag Break flag Register bank 0 flag Register bank 1 flag Register bank 2 flag Register bank 3 flag Vector PC Contents of memory indicated by contents of in parenthesis Displacement (8/16-bit) Temporary register (8/16/32 bits) 16 bits with 8-bit displacement sign-extended Immediate segment data (16 bits) Immediate offset data (16 bits) Transfer direction Addition Subtraction Multiplication Division Modulo Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) 2-digit hexadecimal number 4-digit hexadecimal number Alternate function, or
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Table 17-4. Flag Operation Legend
Identifier (Blank) 0 1 x U R
Description No change Cleared to 0 Set to 1 Set or cleared depending on result Undefined Previously saved value is restored
Table 17-5. Memory Addressing
mem 000 001 010 011 100 101 110 111
mod
00 BW + IX BW + IY BP + IX BP + IY IX IY Direct address BW
01 BW + IX + disp8 BW + IY + disp8 BP + IX + disp8 BP + IY + disp8 IX + disp8 IY + disp8 BP + disp8 BW + disp8
10 BW + IX + disp16 BW + IY + disp16 BP + IX + disp16 BP + IY + disp16 IX + disp16 IY + disp16 BP + disp16 BW + disp16
Note
When BP is used in memory addressing other than in a primitive instruction, the default segment register is SS. When BP is not used, the default segment register is DS0. In primitive instruction memory addressing, the destination block default segment register is DS1. In memory addressing, the source block default segment register is DS0.
Table 17-6. 8/16-Bit General Register Selection
Table 17-7. Segment Register Selection
reg 000 001 010 011 100 101 110 111
W=0 AL CL DL BL AH CH DH BH
W=1 AW CW DW BW SP BP IX IY
sreg 00 01 10 11 DS1 PS SS DS0
Table 17-8. Extended Segment Register Selection
xsreg 10 11 DS3/VPC DS2
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Number of Clock Cycles In the case of a memory operand the number of clock cycles depends on the addressing mode. The following numbers should be used for "EA" in Table 17-9 "Number of Clock Cycles".
mod 00 mem 000 001 010 011 100 101 110 111 BW + IX BW + IY BP + IX BP + IY IX IY Direct address BW Clock Cycles 3 3 3 3 2 2 2 2 01 Clock Cycles 3 3 3 3 2 2 2 2 10 Clock Cycles 3 3 3 3 2 2 2 2
BW + IX + disp8 BW + IY + disp8 BP + IX + disp8 BP + IY + disp8 IX + disp8 IY + disp8 BP + disp8 BW + disp8
BW + IX + disp16 BW + IY + disp16 BP + IX + disp16 BP + IY + disp16 IX + disp16 IY + disp16 BP + disp16 BW + disp16
"T" indicates the number of wait states. Any number of wait states from "0" (no wait) up can be used.
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Table 17-9. Number of Clock Cycles (1/20)
Instruction Group
Bus Width*
Byte Processing On-Chip RAM Access 2 EA + 2 Other Access 2 EA + 3
Word Processing On-Chip RAM Access 2 EA + 2 Other Access 2 EA + 3 EA + 8 + 2T
Mnemonic
Operands
reg, reg' mem, reg
-- -- 8
reg, mem 16 mem, imm reg, imm -- -- 8 acc, dmem 16 dmem, acc sreg, reg16 xsreg, reg16 VPC, reg16 -- -- 8
EA + 2
EA + 5 + T
EA + 2 EA + 5 + T
EA + 2 2
EA + 3 2
EA + 2 2
EA + 3 2 10 + 2T
4
7+T
4 7+T
4 --
5 --
4 2
5 2
Data transfer instructions
-- 16 8
--
2
2
EA + 8 + 2T -- -- EA + 2 EA + 5 + T EA + 8 + 2T -- -- EA + 2 EA + 5 + T -- -- 2 2
MOV
sreg, mem16 16 xsreg,mem16/ VPC, mem16 reg16, sreg reg16, xsreg/ reg16, VPC mem16, sreg mem16, xsreg/ mem16, VPC 8 16 -- 8
-- 16 -- 8 -- 16 8 -- 16 8 -- 16 8 -- 16 8 -- 16 --
--
2
2
--
EA + 2
EA + 3
--
EA + 2
EA + 3
DS0, reg16, mem32
EA + 17 + 4T -- EA + 5 EA + 11 + 2T EA + 17 + 4T -- EA + 5 EA + 11 + 2T EA + 17 + 4T -- EA + 5 EA + 11 + 2T EA + 17 + 4T -- EA + 5 EA + 11 + 2T
DS2, reg16, mem32
DS1, reg16, mem32
DS3, reg16, mem32
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
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Table 17-9. Number of Clock Cycles (2/20)
Instruction Group
Bus Width*
Byte Processing On-Chip RAM Access 2 3 2 -- 6 4 Other Access 2 3 --
Word Processing On-Chip RAM Access -- Other Access --
Mnemonic
Operands
AH, PSW MOV PSW, AH
-- 8 16
--
2 -- 9+T 4 EA + 2 -- 4 EA + 2 -- 4 EA + 10 + 2T
Data transfer instructions
LDEA TRANS/ TRANSB
reg16, mem16 src-table reg, reg' mem, reg/ reg, mem AW, reg16/ reg16, AW
-- -- --
XCH
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T
-- --
-- -- -- 0 to 1 0 to 1
-- -- -- 0 to 1 0 to 1
4 8 9 0 to 1 0 to 1
4 8 9 0 to 1 0 to 1
MOVSPA MOVSPB REPC Repeat prefixes REPNC REP/ REPE/ REPZ REPNE/ REPNZ MOVBK dst-block, src-block reg16
-- -- --
--
0 to 1
0 to 1
0 to 1
0 to 1
--
0 to 1
0 to 1
0 to 1 21 + 2T
0 to 1 22 + 2T 9 + (18 + 4T)n 5 19 + T 9 + (12 + 2T)n 5 28 + 4T 9 + (21 + 4T)n 5 22 + 2T 9 + (15 + 2T)n 5
18 + T 8 (rep) 9 + (11 + T)n
19 + T 9 + (14 + 2T)n 5 9 + (12 + 2T)n 18 + T
Primitive block transfer instructions
MOVBKB/ MOVBKW 16
(rep CW = 0) 5 5
9 + (11 + T)n 5 23 + 2T
CMPBK
src-block, dst-block 8
20 + T
22 + 2T 9 + (16 + 2T)n
(rep) 9 + (13 + T)n CMPBKB/ CMPBKW 16 (rep CW = 0) 5
5 9 + (15 + 2T)n 20 + T 9 + (13 + T)n 5 5
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width n: Number of repetitions
Remark
86
PD70433
Table 17-9. Number of Clock Cycles (3/20)
Instruction Group
Bus Width*
Byte Processing On-Chip RAM Access Other Access
Word Processing On-Chip RAM Access Other Access 20 + T
Mnemonic
Operands
CMPM
dst-block 15 8 (rep) 10 + 7n (rep CW = 0) 5 5 5 17 + T 15
10 + (12 + 2T)n 5 10 + (9 + T)n 10 + 7n 17 + T
CMPMB/ CMPMW 16
10 + (9 + T)n 5 16 + T
Primitive block transfer instructions
LDM
src-block 10 8 (rep) 9 + 3n (rep CW = 0) 5 5 5 13 + T 10
9 + (9 + 2T)n 5 9 + (6 + T)n 9 + 3n 13 + T
LDMB/ LDMW 16
9 + (6 + T)n 5 13
STM
dst-block 12 8 (rep) 9 + 5n (rep CW = 0) 5 8 5 5 13 12
9 + (9 + 2T)n 5 9 + (6 + T)n 9 + 5n 13
STMB/ STMW 16
9 + (6 + T)n 5 31 to 72
Bit field manipulation instructions
reg8, reg8' 16 INS 8 reg8, imm4 16 8 reg8, reg8' 16 EXT 8 reg8, imm4 16
--
--
22 to 63 23 to 64 31 to 72
--
--
22 to 63 23 to 64 19 + 2T to 48 + 4T
--
--
19 to 41 19 to 42 + 2T 19 + 2T to 48 + 4T
--
--
19 to 41 19 to 42 + 2T
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
n: Number of repetitions
87
PD70433
Table 17-9. Number of Clock Cycles (4/20)
Bus Width *1
Instruction Group
Byte Processing On-Chip RAM Access Other Access
Word Processing On-Chip RAM Access Other Access 10 + 2T
Mnemonic
Operands
8 acc8, imm8 Input/output instructions 16 IN*2 8 acc, DW 16 8 imm8, acc 16 OUT*2 8 DW, acc 16 20 + 2T 17 + T 8 (rep) 9 + (10 + T)n (rep CW = 0) 5 5 18 + T 9 + (13 + 2T)n 5 9 + (11 + 2T)n 17 + T 16 9 + (10 + T)n 5 17 + 2T 14 + T 8 (rep) 9 + (7 + T)n (rep CW = 0) 5 5 17 + 2T 9 + (10 + 2T)n 5 9 + (10 + 2T)n 14 + T 16 9 + (7 + T)n 5 -- 5 -- -- 5 -- -- 7+T -- -- 7+T --
7+T 10 + 2T 7+T
5
5
21 + 2T 9 + (17 + 4T)n 5 18 + T 9 + (11 + 2T)n 5 23 + 4T 9 + (16 + 4T)n 5 17 + 2T 9 + (10 + 2T)n 5
Primitive input/output instructions
INM*2
dst-block, DW
OUTM*2
DW, src-block
* 1. 8
: 8-bit width
16 : 16-bit width 2. When IBRK = 1. As shown in the next page when IBRK = 0. Remark n: Number of repetitions
88
PD70433
Table 17-9. Number of Clock Cycles (5/20)
Bus Width*
Instruction Group
Byte Processing On-Chip RAM Access Other Access 60 + 10T -- -- 40 + 5T 60 + 10T -- -- 40 + 5T 60 + 10T -- -- 40 + 5T 60 + 10T -- -- 40 + 5T 60 + 10T -- -- 40 + 5T 60 + 10T -- -- 40 + 5T
Word Processing On-Chip RAM Access Other Access 60 + 10T 40 + 5T 60 + 10T 40 + 5T 60 + 10T 40 + 5T 60 + 10T 40 + 5T 60 + 10T 40 + 5T 60 + 10T 40 + 5T
Mnemonic
Operands
8 acc8, imm8 16 Input/output instructions IN 8 acc, DW 16 8 imm8, acc 16 OUT 8 DW, acc 16 Primitive input/ output instructions 8 INM dst-block, DW 16 8 OUTM DW, src-block 16
*
8 : 8-bit width 16 : 16-bit width
89
PD70433
Table 17-9. Number of Clock Cycles (6/20)
Bus Width*
Instruction Group
Byte Processing On-Chip RAM Access 3 Other Access 3
Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T
Mnemonic
Operands
reg, reg'
-- 8
mem, reg 16 8 reg, mem ADD reg, imm 16 -- 8 mem, imm 16 acc, imm reg, reg' Addition/subtraction instructions -- -- 8 mem, reg 16 8 ADDC reg, mem 16 reg, imm -- 8 mem, imm 16 acc, imm reg, reg' -- -- 8 mem, reg 16 8 reg, mem SUB reg, imm 16 -- 8 mem, imm 16 acc, imm --
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T EA + 9 + 2T
EA + 2
EA + 6 + T
EA + 2 EA + 6 + T
2
2
2
2 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T
2 3
2 3
2 3
2 3 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T EA + 9 + 2T
EA + 2
EA + 6 + T
EA + 2 EA + 6 + T
2
2
2
2 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T
2 3
2 3
2 3
2 3 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T EA + 9 + 2T
EA + 2
EA + 6 + T
EA + 2 EA + 6 + T
2
2
2
2 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T
2
2
2
2
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
90
PD70433
Table 17-9. Number of Clock Cycles (7/20)
Bus Width*
Instruction Group
Byte Processing On-Chip RAM Access 3 Other Access 3
Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T
Mnemonic
Operands
reg, reg' Addition/subtraction instructions
-- 8
mem, reg 16 8 reg, mem SUBC reg, imm 16 -- 8 mem, imm 16 acc, imm dst-string, src-string -- 8
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T EA + 9 + 2T
EA + 2
EA + 6 + T
EA + 2 EA + 6 + T
2
2
2
2 EA + 10 + 2T
EA + 4
EA + 7 + T
EA + 4 EA + 7 + T
2
2
2
2
ADD4S
6 + (15 + T)n 16 8 6 + (16 + T)n 16 8 6 + (15 + T)n 16 8 16 8 16 -- 8 5 EA + 5 5 EA + 5 2
6 + (19 + 3T)n
--
--
BCD operation instructions
SUB4S
dst-string, src-string
6 + (20 + 3T)n
--
--
CMP4S
dst-string, src-string reg8
6 + (18 + 2T)n
--
--
5 EA + 8 + T 5 EA + 8 + T 2
-- -- -- -- --
-- -- -- -- -- EA + 10 + 2T
ROL4 mem8 reg8 ROR4 mem8 reg8
Increment/decrement instructions
INC
mem 16 reg16 reg8 -- -- 8
EA + 3
EA + 7 + T
EA + 3 EA + 7 + T
-- 2
-- 2
2 --
2 -- EA + 10 + 2T
DEC
mem 16 reg16 --
EA + 3
EA + 7 + T
EA + 3 EA + 7 + T
--
--
2
2
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
n: Half of number of BCD digits
91
PD70433
Table 17-9. Number of Clock Cycles (8/20)
Bus Width*
Instruction Group
Byte Processing On-Chip RAM Access 11 Other Access 11
Word Processing On-Chip RAM Access 15 Other Access 15 EA + 21 + 2T
Mnemonic
Operands
reg8
-- 8
mem8 16 MULU reg16 -- 8 mem16 16 reg8 Multiplication instructions -- 8 mem8 16 reg16 -- 8 mem16 16 MUL reg16, reg16', imm8/reg16, imm8 reg16, mem16, imm8 reg16, reg16', imm16/reg16, imm16 reg16, mem16, imm1616
EA + 12
EA + 14 + T
EA + 16 EA + 18 + T
11
11
15
15 EA + 21 + 2T
EA + 12
EA + 14 + T
EA + 16 EA + 18 + T
10
10
14
14 EA + 20 + 2T
EA + 11
EA + 13 + T
EA + 15 EA + 17 + T
10
10
14
14 EA + 20 + 2T
EA + 11
EA + 13 + T
EA + 15 EA + 17 + T
--
--
--
14
14
8 -- 16 -- EA + 15
EA + 20 + 2T EA + 17 + T
--
--
--
14
14
8 -- -- EA + 15
EA + 20 + 2T EA + 17 + T
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
92
PD70433
Table 17-9. Number of Clock Cycles (9/20)
Bus Width*
Instruction Group
Byte Processing On-Chip RAM Access 15/62 + 10T 15/42 + 5T EA + 16/63 + 10T EA + 16/43 + 5T 15/62 + 10T 15/42 + 5T EA + 16/63 + 10T EA + 16/43 + 5T 17/64 + 10T 17/44 + 5T EA + 18/65 + 10T EA + 18/45 + 5T 17/64 + 10T 17/44 + 5T EA + 18/65 + 10T EA + 18/45 + 5T 6 9 -- Other Access 15/62 + 10T 15/42 + 5T EA + 18 + T/63 + 10T EA + 18 + T/63 + 5T 15/62 + 10T 15/42 + 5T EA + 18 + T/63 + 10T EA + 18 + T/43 + 5T 17/64 + 10T 17/44 + 5T EA + 20 + T/65 + 10T EA + 20 + T/45 + 5T 17/64 + 10T 17/44 + 5T EA + 20 + T/65 + 10T EA + 20 + T/45 + 5T
Word Processing On-Chip RAM Access 23/57 + 10T 23/42 + 5T EA + 24/58 + 10T EA + 24/43 + 5T 23/57 + 10T 23/42 + 5T EA + 24/58 + 10T EA + 24/43 + 5T 25/59 + 10T 25/44 + 5T EA + 26/60 + 10T EA + 26/45 + 5T 25/59 + 10T 25/44 + 5T EA + 26/60 + 10T EA + 26/45 + 5T Other Access 23/57 + 10T 23/42 + 5T EA + 30 + 2T/58 + 10T EA + 26 + T/43 + 5T 23/57 + 10T 23/42 + 5T EA + 30 + 2T/58 + 10T EA + 26 + T/43 + 5T 25/59 + 10T 25/44 + 5T EA + 31 + 2T/60 + 10T EA + 28 + T/45 + 5T 25/59 + 10T 25/44 + 5T EA + 31 + 2T/60 + 10T EA + 28 + T/45 + 5T
Mnemonic
Operands
8 reg8 16 8 mem8 DIVU reg16 16 Division instructions 8 mem16 16 8 reg8 16 8 mem8 16 DIV 8 reg16 16 8 mem16 16 BCD adjustment instructions 8 ADJBA 16 ADJ4A -- 8 ADJBS 16 ADJ4S CVTBD Data conversion instructions CVTDB CVTBW CVTWL -- -- -- -- -- 16 8
--
9 3 6 9 3 18 8 3 -- 3 6 -- 9 3 18 8 3 -- -- -- -- -- 3 -- -- -- -- 3 -- -- --
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
Figures on right of / (slash) apply in case of a divide error.
93
PD70433
Table 17-9. Number of Clock Cycles (10/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 9 + 2T EA + 4 16 8 CMP reg, mem 16 reg, imm -- 8 mem, imm 16 acc, imm reg Complement operation instructions NOT mem 16 reg NEG mem 16 reg, reg' mem, reg/ reg, mem TEST reg, imm -- 8 EA + 4 16 -- 8 mem, imm Logical operation instructions 16 acc, imm reg, reg' -- -- 8 mem, reg 16 8 AND reg, mem 16 reg, imm -- 8 mem, imm 16 acc, imm -- 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 2 2 2 EA + 2 EA + 6 + T EA + 2 EA + 6 + T 2 EA + 10 + 2T EA + 4 EA + 7 + T EA + 4 EA + 7 + T EA + 9 + 2T 2 3 2 3 2 3 EA + 4 EA + 6 + T EA + 4 EA + 6 + T 2 3 EA + 10 + 2T 2 2 2 EA + 6 + T EA + 4 EA + 6 + T 2 EA + 9 + 2T 3 3 3 -- 8 EA + 3 EA + 7 + T EA + 3 EA + 7 + T 3 EA + 9 + 2T 2 2 2 -- -- 8 EA + 3 EA + 7 + T EA + 3 EA + 7 + T 2 EA + 10 + 2T 2 2 2 2 2 2 EA + 4 EA + 6 + T EA + 4 EA + 6 + T 2 2 EA + 10 + 2T 2 2 2 EA + 2 EA + 6 + T EA + 2 EA + 6 + T 2 EA + 9 + 2T EA + 6 + T EA + 4 EA + 6 + T EA + 9 + 2T
Mnemonic
Operands
reg, reg'
-- 8
mem, reg Comparison instructions
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
94
PD70433
Table 17-9. Number of Clock Cycles (11/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T EA + 4 16 8 reg, mem OR reg, imm Logical operation instructions 16 -- 8 mem, imm 16 acc, imm reg, reg' -- -- 8 mem, reg 16 8 reg, mem XOR reg, imm 16 -- 8 mem, imm 16 acc, imm reg8, CL -- -- 8 mem8, CL 16 Bit manipulation instructions reg16, CL -- 8 mem16, CL 16 TEST1 reg8, imm3 -- 8 mem8, imm3 16 reg16, imm4 -- 8 mem16, imm4 16 EA + 4 EA + 6 + T EA + 4 EA + 6 + T 2 2 2 EA + 4 EA + 6 + T EA + 4 EA + 6 + T 2 EA + 9 + 2T 2 2 2 2 EA + 9 + 2T EA + 4 EA + 6 + T EA + 4 EA + 6 + T 3 3 3 EA + 4 EA + 6 + T EA + 4 EA + 6 + T 3 EA + 9 + 2T 2 3 2 3 2 3 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 3 EA + 9 + 2T 2 2 2 EA + 2 EA + 6 + T EA + 2 EA + 6 + T 2 EA + 10 + 2T EA + 4 EA + 7 + T EA + 4 EA + 7 + T EA + 9 + 2T 2 3 2 3 2 3 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 3 EA + 10 + 2T 2 2 2 EA + 2 EA + 6 + T EA + 2 EA + 6 + T 2 EA + 10 + 2T EA + 7 + T EA + 4 EA + 7 + T EA + 9 + 2T
Mnemonic
Operands
reg, reg'
-- 8
mem, reg
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
95
PD70433
Table 17-9. Number of Clock Cycles (12/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T EA + 4 16 reg16, CL -- 8 mem16, CL 16 NOT1 reg8, imm3 -- 8 mem8, imm3 16 reg16, imm4 Bit manipulation instructions -- 8 mem16, imm4 16 CY reg8, CL -- -- 8 mem8, CL 16 reg16, CL -- 8 mem16, CL 16 CLR1 reg8, imm3 -- 8 mem8, imm3 16 reg16, imm4 -- 8 mem16, imm4 16 CY DIR -- -- 2 2 2 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 2 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 EA + 10 + 2T 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 EA + 10 + 2T 3 3 3 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 3 EA + 10 + 2T 2 3 2 3 2 3 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 3 EA + 10 + 2T 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 EA + 10 + 2T 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 EA + 10 + 2T 3 3 3 EA + 7 + T EA + 4 EA + 7 + T 3 EA + 10 + 2T
Mnemonic
Operands
reg8, CL
-- 8
mem8, CL
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
96
PD70433
Table 17-9. Number of Clock Cycles (13/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T EA + 4 16 reg16, CL -- 8 mem16, CL Bit manipulation instructions 16 reg8, imm3 SET1 8 mem8, imm3 16 reg16, imm4 -- 8 mem16, imm4 16 CY DIR -- -- 8 mem BSCH reg reg, 1 16 -- -- 8 mem, 1 16 Shift instructions reg, CL SHL mem, CL 16 reg, imm8 -- 8 mem, imm8 16 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 3 EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n EA + 8 + 3n + T 4 + 3n 3 EA + 8 + 3n + T 4 + 3n 3 EA + 8 + 3n + T 4 + 3n 3 EA + 8 + 3n + T 4 + 3n 3 EA + 10 + 2T 2 2 EA + 8 + 3n + T 2 2 EA + 8 + 3n + T 2 2 EA + 11 + 3n + 2T EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 2 EA + 11 + 3n + 2T 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 EA + 10 + 2T EA + 10 + 2T -- 2 2 2 EA + 4 EA + 7 + T EA + 4 EA + 7 + T 2 3 3 3 EA + 7 + T EA + 4 EA + 7 + T 3 EA + 10 + 2T
Mnemonic
Operands
reg8, CL
-- 8
mem8, CL
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
Number of shifts (n in a bit manipulation instruction indicates the bit number searched for)
97
PD70433
Table 17-9. Number of Clock Cycles (14/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T EA + 3 16 reg, CL SHR mem, CL 16 reg, imm8 Shift instructions -- 8 mem, imm8 16 reg, 1 -- 8 mem, 1 16 reg, CL SHRA mem, CL 16 reg, imm8 -- 8 mem, imm8 16 reg, 1 -- 8 mem, 1 Rotate instructions 16 reg, CL ROL mem, CL 16 reg, imm8 -- 8 mem, imm8 16 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 3 EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n 3 3 3 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 3 EA + 10 + 2T 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 3 EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n 3 3 3 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 3 EA + 10 + 2T 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n
Mnemonic
Operands
reg, 1
-- 8
mem, 1
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
Number of shifts (n in a bit manipulation instruction indicates the bit number searched for)
98
PD70433
Table 17-9. Number of Clock Cycles (15/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access 3 Other Access 3 Word Processing On-Chip RAM Access 3 Other Access 3 EA + 10 + 2T EA + 3 16 reg, CL ROR mem, CL 16 reg, imm8 -- 8 mem, imm8 16 reg, 1 -- 8 mem, 1 16 Rotate instructions reg, CL ROLC mem, CL 16 reg, imm8 -- 8 mem, imm8 16 reg, 1 -- 8 mem, 1 16 reg, CL RORC mem, CL 16 reg, imm8 -- 8 mem, imm8 16 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 3 EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n 3 3 3 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 3 EA + 10 + 2T 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 3 EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n 3 3 3 EA + 6 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 3 EA + 10 + 2T 5+n 5+n 5+n -- 8 EA + 5 + n EA + 8 + T + n EA + 6 + n EA + 8 + T + n 5+n EA + 11 + 2T + n 5+n 5+n 5+n EA + 7 + T EA + 3 EA + 7 + T 5+n EA + 11 + 2T + n
Mnemonic
Operands
reg, 1
-- 8
mem, 1
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
Remark
Number of shifts
99
PD70433
Table 17-9. Number of Clock Cycles (16/20)
Bus Width *1 Instruction Group Byte Processing On-Chip RAM Access Other Access Word Processing On-Chip RAM Access Other Access 19 + 2T -- 16 8 regptr16 16 8 CALL Subroutine control instructions memptr16 16 8 far-proc 16 8 memptr32 16 8 -- 16 8 pop-value 16 RET 8 *2 16 8 pop-value*2 16 8 mem16 16 Stack manipulation instructions reg16 sreg xsreg/VPC PUSH PSW -- 8 R 16 imm8 imm16 -- -- -- -- -- -- -- -- -- -- -- 36 + 7T 6 6 -- -- -- 6 57 + 14T -- -- -- -- -- -- -- -- -- -- -- -- -- -- EA + 7 EA + 10 + T 7 7 7 -- -- -- 21 + 2T EA + 13 + 2T -- -- -- 20 + 2T 27 + 4T 26 + 4T -- -- -- 16 + T -- -- 15 + T 19 + 2T -- -- EA + 26 + 2T EA + 32 + 4T 18 + 2T EA + 32 + 4T -- -- -- 23 + 2T EA + 44 + 8T -- -- EA + 16 + T EA + 18 + 2T 29 + 4T EA + 19 + 2T -- -- -- 15 + T EA + 24 + 4T -- -- 16 + T 18 + 2T
Mnemonic
Operands
8 near-proc
* 1. 8
: 8-bit width
16 : 16-bit width -- : Both 8-bit and 16-bit bus width 2. Segment-external Remark n: Number of shifts
100
PD70433
Table 17-9. Number of Clock Cycles (17/20)
Bus Width *1 Instruction Group Byte Processing On-Chip RAM Access Other Access Word Processing On-Chip RAM Access EA + 13 + 2T -- 16 8 reg16 16 Stack manipulation instructions 8 sreg 16 POP 8 xsreg/VPC 16 8 PSW 16 8 R 16 PREPARE*2 imm16, imm8 -- 8 DISPOSE 16 near-label short-label Branch instructions regptr16 -- -- -- 8 BR memptr16 16 far-label -- 8 memptr32 16 -- -- EA + 12 EA + 18 + 2T -- -- -- -- -- EA + 9 EA + 11 + T 9 EA + 24 + 4T -- -- -- -- -- -- -- -- -- -- -- -- 7+T 9 9 8 EA + 14 + 2T --- -- -- -- -- 52 + 8T 9 10 + 2T -- -- -- 8+T 76 + 16T -- -- -- 7+T 11 + 2T 10 + 2T -- -- -- 7+T -- -- -- 7+T 10 + 2T -- EA + 10 + T EA + 11 + T 10 + 2T Other Access EA + 14 + 2T
Mnemonic
Operands
8 mem16
* 1. 8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width 2. When imm8 = 0. As shown below when imm8 1.
8 PREPARE imm16, imm8 16 -- -- -- 14 + (12 + T)n 15+2T+(16+4T)n
n : imm8
101
PD70433
Table 17-9. Number of Clock Cycles (18/20)
Bus Width* Instruction Group Byte Processing On-Chip RAM Access -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Other Access -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Word Processing On-Chip RAM Access 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 10/5 10/5 10/5 10/5 Other Access 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 9/3 10/5 10/5 10/5 10/5
Mnemonic
Operands
BV BNV BC/BL BNC/BNL BE/BZ BNE/BNZ BNH BH Conditional branch instructions BN BP BPE BPO BLT BGE BLE BGT DBNZNE DBNZE DBNZ BCWZ
short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label sfr, imm3 short-label
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8
BTCLR
-- 16 8 -- 16
21/14
--
--
BTCLRL
sfrl, imm3 short-label
20/13
--
--
*
8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width
102
PD70433
Table 17-9. Number of Clock Cycles (19/20)
Bus Width *1 Instruction Group Byte Processing On-Chip RAM Access Other Access Word Processing On-Chip RAM Access Other Access 50 + 10T -- 16 BRK*2 8 imm8 (3) 16 Interrupt instructions 8 BRKV*2 16 8 RETI 16 RETRBI FINT -- -- 8 CHKIND*3 16 BRKCS *4 TSKSW HALT CPU control instructions STOP IDLE POLL DI EI BUSLOCK reg16 -- -- -- -- -- -- -- -- -- -- -- -- -- 3 3 0 to 1 -- -- -- -- -- 3 3 0 to 1 13 -- -- -- -- 3 3 0 to 1 13 -- -- -- -- 3 3 0 to 1 reg16 -- -- -- 12 -- -- EA + 11 EA + 15 + 2T 12 -- 3 -- 3 -- 3 -- -- -- 22 + 2T 9 3 EA + 21 + 4T -- -- -- 37 + 4T + t 28 + 4T -- -- -38 + 4T + t 51 + 10 T 52 + 10T -- -- 36 + 4T + t
Mnemonic
Operands
8 3
* 1. 8 : 8-bit width 16 : 16-bit width -- : Both 8-bit and 16-bit bus width 2. When BRK = 1, add 50 + 10T in case of 8-bit bus width, and 34 + 4T in case of 16-bit bus. 3. When (mem32) > reg16 or (mem32 + 2) < reg16, add 50 + 10T in case of 8-bit bus width, and 34 + 4T + t in case of 16-bit bus width. 4. Register bank switching instructions Remarks When T 2, t = T - 1
103
PD70433
Table 17-9. Number of Clock Cycles (20/20)
Bus Width *1 Instruction Group Byte Processing On-Chip RAM Access Other Access Word Processing On-Chip RAM Access Other Access 50 + 10T -- 16 CPU control instructions FPO1 8 fp-op, mem 16 8 fp-op 16 FPO2 8 fp-op, mem 16 NOP -- 8 *2 RSTWDT imm8, imm8' 16 *4
Queue manipulation instructions
Mnemonic
Operands
8 fp-op -- --
36 + 4T + t EA + 50 + 10 T -- -- -- EA + 36 + 4T + t 50 + 10T -- -- -- 36 + 4T + t EA + 50 + 10 T -- -- -- EA + 36 + 4T + t 4 4 9/54 + 10T*3 -- 9/40 + 4T + t*3 0 to 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 to 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 to 1 -- -- -- -- -- -- -- -- -- -- -- -- 0 to 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 4
-- QHOUT QOUT QTIN ALBIT COLTRP imm16 imm16 imm16 -- -- -- -- -- -- -- -- -- -- -- --
Dedicated fax instructions
MHENC MRENC SCHEOL GETBIT MHDEC MRDEC CNVTRP
* 1. 8
: 8-bit width
16 : 16-bit width -- : Both 8-bit and 16-bit bus width 2. Watchdog timer manipulation instruction 3. Figure after / (slash) applies when word processing is performed during data error. When T 2, t = T - 1 4. Segment override prefix instructions (DS0:, DS1:, PS:, SS:) Extended segment override prefix instructions (DS2: DS3:) Register file space access override prefix instruction (IRAM)
104
17.3 INSTRUCTION SET TABLE
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg, reg' mem, reg reg, mem mem, imm reg, imm acc, dmem 1 0 0 0 1 0 1W 1 0 0 0 1 0 0W 1 0 0 0 1 0 1W 1 1 0 0 0 1 1W 1 0 1 1 W reg 1 0 1 0 0 0 0W 76543210 11 reg reg' mem mem 2 2 to 4 2 to 4 3 to 6 2 to 3 3 regreg' (mem)reg reg(mem) (mem)imm regimm If W = 0, AL(dmem) If W = 1, AH(dmem + 1), AL(dmem) If W = 0, (dmem) AL If W = 1, (dmem + 1)AH, (dmem)AL sregreg16 xsregreg16 sreg(mem16) xsreg(mem16) reg16sreg reg16xsreg (mem16)sreg (mem16)xsreg reg16(mem32) DS0(mem32 + 2) reg16(mem32) DS1(mem32 + 2) reg16(mem32) DS2(mem32 + 2) sreg : SS, DS0, DS1 xsreg : DS2, DS3 sreg : SS, DS0, DS1 Bytes Operation
Flags AC CY V P S Z
mod reg mod reg
mod0 0 0 mem
dmem, acc sreg, reg16 xsreg, reg16* sreg, mem16 MOV xsreg, mem16* reg16, sreg reg16, xsreg* mem16, sreg mem16, xsreg* DS0, reg16, mem32 DS1, reg16, mem32 DS2, reg16*, mem32
1 0 1 0 0 0 1W 10001110 10001110 10001110 10001110 10001100 10001100 10001100 10001100 11000101 11000100 00001111 mod reg mem 00110110 1 1 0 sreg 1 1 1 xsreg mod 0 sreg reg reg mem
3 2 2 2 to 4 2 to 4 2 2 2 to 4 2 to 4 2 to 4 2 to 4
Data transfer instructions
mod 1 xsreg mem 1 1 0 sreg 1 1 1 xsreg mod 0 sreg reg reg mem
mod 1 xsreg mem mod reg mod reg mem mem
00111110 3 to 5
PD70433
DS3, reg16*, mem32
00001111 mod reg mem
3 to 5
reg16(mem32) DS3(mem32 + 2)
105
*
This instruction is newly added to the V25 or V35.
Instruction Group
Data transfer instructions
Repeat prefixes
106
Operation Code Mnemonic Operand(s) 76543210 AH, PSW MOV PSW, AH LDEA TRANS TRANSB*1 reg16, mem16 src-table reg, reg' XCH mem, reg reg, mem AW, reg16 reg16, AW 10011110 10001101 11010111 1 0 0 0 0 1 1W 1 0 0 0 0 1 1W 10010 reg 00100101 10010101 3 11111 reg 11 reg reg' mem mod reg mem 1 2 to 4 1 2 2 to 4 1 2 S, Z, F1, AC, F0, P, IBRK, CYAH reg16mem16 AL(BW + AL) regreg' (mem)reg AWreg16 New register bank SS, SP Old register bank SS, SP SS, SP of register bank indicated by reg16 current register bank SS, SP While CW 0, the following byte primitive block transfer instruction is executed and CW is decremented (-1). If there is a pending interrupt, it is serviced. If CY 1, the loop is exited. Same as above. If CY 0, the loop is exited. While CW 0, the following byte primitive block transfer instruction is executed and CW is decremented (-1). If there is a pending interupt, it is serviced. If the primitive block transfer instruction is CMPBK or CMPM, and Z 1, the loop is exited. Same as above. If Z 0, the loop is exited. x x 10011111 76543210 1 AHS, Z, F1, AC, F0, P, IBRK, CY Bytes Operation
Flags AC CY V P S Z
x
x
x
mod reg
MOVSPA*2
00001111 00001111
MOVSPB*2
reg16
REPC
01100101
1
REPNC
01100100
1
REP REPE REPZ REPNE REPNZ 11110011 1
11110010
1
PD70433
* 1. The operand can be omitted in the case of the TRANS instruction. The TRANSB instruction has no operand. 2. This instruction is newly added to the V20 or V30.
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 76543210 If W = 0, (IY)(IX) DIR = 0: IXIX + 1, IYIY + 1 DIR = 1: IXIX - 1, IYIY - 1 1 0 1 0 0 1 0W 1 If W = 1, (IY + 1, IY)(IX + 1, IX) DIR = 0: IXIX + 2, IYIY + 2 DIR = 1: IXIX - 2, IYIY - 2 If W = 0, (IX) - (IY) DIR = 0: IXIX + 1, IYIY + 1 DIR = 1: IXIX - 1, IYIY - 1 1 0 1 0 0 1 1W 1 If W = 1, (IX + 1, IX) - (IY + 1, IY) DIR = 0: IXIX + 2, IYIY + 2 DIR = 1: IXIX - 2, IYIY - 2 If W = 0, AL - (IY) DIR = 0: IYIY + 1 ; DIR = 1: IYIY - 1 dst-block 1 0 1 0 1 1 1W 1 If W = 1, AW - (IY + 1, IY) DIR = 0: IYIY + 2 ; DIR = 1: IYIY - 2 If W = 0, AL(IX) DIR = 0: IXIX + 1 ; DIR = 1: IXIX - 1 src-block 1 0 1 0 1 1 0W 1 If W = 1, AW + (IX + 1, IX) DIR = 0: IX + 2 ; DIR = 1: IXIX - 2 If W = 0, (IY)AL DIR = 0: IYIY + 1 ; DIR = 1: IYIY - 1 dst-block 1 0 1 0 1 0 1W 1 If W = 1, AW - (IY + 1, IY)AW DIR = 0: IYIY + 2 ; DIR = 1: IYIY - 2 x x x x Bytes Operation
Flags AC CY V P S Z
MOVBK MOVBKB MOVBKW
dst-block, src-block
Primitive block transfer instructions
CMPBK CMPBKB CMPBKW
src-block, dst-block
x
x
x
x
CMPM CMPMB CMPMW
x
x
x
x
LDM LDMB LDMW
STM STMB STMW
PD70433
107
Instruction Group
Bit field manipulation instructions
Input/output instructions
Primitive input /output instructions
108
Operation Code Mnemonic Operand(s) 76543210 00001111 reg8, reg8' 11 INS 00001111 reg8, imm4 11000 reg 00110011 3 11 EXT 00001111 reg8, imm4 11000 acc, imm8 IN* acc, DW 1 1 1 0 1 1 0W 1 If W = 0, AL(DW) If W = 1, AH(DW + 1), AL(DW) If W = 0, (imm8)AL If W = 1, (imm8 + 1)AH, (imm8)AL If W = 0, (DW)AL If W = 1, (DW + 1)AH, (DW)AL If W = 0, (IY)(DW) DIR = 0: IYIY + 1 ; DIR = 1: IYIY - 1 0 1 1 0 1 1 0W 1 If W = 1, (IY + 1, IY)(DW + 1, DW) DIR = 0: IYIY + 2 ; DIR = 1: IYIY - 2 If W = 0, (DW)(IX) DIR = 0: IXIX + 1 ; DIR = 1: IXIX - 1 0 1 1 0 1 1 1W 1 If W = 1, (DW + 1, DW)(IX + 1, IX) DIR = 0: IXIX + 2 ; DIR = 1: IXIX - 2 reg 2 If W = 0, AL(imm8) If W = 1, AH(imm8 + 1), AL(imm8) 00111011 4 AW16-bit field reg' reg AW16-bit field 00111001 4 16-bit fieldAW reg' reg 76543210 00110001 3 16-bit fieldAW Bytes Operation
Flags AC CY V P S Z
00001111 reg8, reg8'
1 1 1 0 0 1 0W
imm8, acc OUT* DW, acc
1 1 1 0 0 1 1W
2
1 1 1 0 1 1 1W
1
INM*
dst-block, DW
OUTM*
DW, src-block
PD70433
*
When IBRK = 0, a software interrupt is generated automatically and the instruction is not executed.
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg, reg' mem, reg reg, mem ADD reg, imm mem, imm acc, imm reg, reg' mem, reg reg, mem ADDC reg, imm mem, imm acc, imm reg, reg' mem, reg reg, mem SUB reg, imm mem, imm acc, imm reg, reg' mem, reg reg, mem SUBC reg, imm mem, imm acc, imm 1 0 0 0 0 0 sW 1 0 0 0 0 0 sW 0 0 0 1 1 1 0W 11011 reg 3 to 4 3 to 6 2 to 3 regreg - imm - CY (mem)(mem) - imm - CY If W = 0, ALAL - imm - CY If W = 1, AWAW - imm - CY mod 0 1 1 mem 1 0 0 0 0 0 sW 1 0 0 0 0 0 sW 0 0 1 0 1 1 0W 0 0 0 1 1 0 1W 0 0 0 1 1 0 0W 0 0 0 1 1 0 1W 11 reg reg' mem mem 11101 reg 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 regreg - imm (mem)(mem) - imm If W = 0, ALAL - imm If W = 1, AWAW - imm regreg - reg' - CY (mem)(mem) - reg - CY regreg - (mem) - CY mod 1 0 1 mem 1 0 0 0 0 0 sW 1 0 0 0 0 0 sW 0 0 0 1 0 1 0W 0 0 1 0 1 0 1W 0 0 1 0 1 0 0W 0 0 1 0 1 0 1W 11 reg reg' mem mem 11010 reg 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 regreg + imm + CY (mem)(mem) + imm + CY If W = 0, ALAL + imm + CY If W = 1, AWAW + imm + CY regreg - reg' (mem)(mem) - reg regreg - (mem) mod 0 1 0 mem 1 0 0 0 0 0 sW 1 0 0 0 0 0 sW 0 0 0 0 0 1 0W 0 0 0 1 0 0 1W 0 0 0 1 0 0 0W 0 0 0 1 0 0 1W 11 reg reg' mem mem 11000 reg 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 regreg + imm (mem)(mem) + imm If W = 0, ALAL + imm If W = 1, AWAW + imm regreg + reg' + CY (mem)(mem) + reg + CY regreg + (mem) + CY mod 0 0 0 mem 0 0 0 0 0 0 1W 0 0 0 0 0 0 0W 0 0 0 0 0 0 1W 76543210 11 reg reg' mem mem 2 2 to 4 2 to 4 regreg + reg' (mem)(mem) + reg regreg + (mem) Bytes Operation
Flags AC CY V x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x P x x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x x x x
mod reg mod reg
mod reg mod reg
Addition/subtraction instructions
mod reg mod reg
mod reg mod reg
PD70433
109
Instruction Group
BCD operation instructions
Increment/decrement instructions
110
Operation Code Mnemonic Operand(s) 76543210 ADD4S*1 SUB4S*1 CMP4S*1 (dst-string, src-string) (dst-string, src-string) (dst-string, src-string) reg8 00001111 00001111 00001111 00001111 11000 ROL4 mem8 00001111 mod 0 0 0 mem reg8 00001111 11000 ROR4 mem8 00001111 mod 0 0 0 mem reg8 INC mem reg16 reg8 DEC mem reg16 11111110 1 1 1 1 1 1 1W 01000 reg 11001 reg 11000 reg 2 2 to 4 1 2 2 to 4 1 reg8reg8 + 1 (mem)(mem) + 1 reg16reg16 + 1 reg8reg8 - 1 (mem)(mem) - 1 reg16reg16 - 1 x x x x x x 00101010 3 to 5 reg
mem
Flags Bytes Operation AC CY V 2 2 2 3 dst BCD stringdst BCD string + src BCD string*2 dst BCD stringdst BCD string - src BCD string*2 dst BCD string - src BCD string*2
reg
76543210 00100000 00100010 00100110 00101000
P U U U
S U U U
Z x x x
U U U
x x x
U U U
AL L
Highorder
Loworder
reg 00101000 3 to 5
mem
AL L
Highorder
Loworder
00101010
3
reg
AL L
Highorder
Loworder
AL L
Highorder
Loworder
x x x x x x
x x x x x x
x x x x x x
x x x x x x
mod 0 0 0 mem
11111110 1 1 1 1 1 1 1W 01001 reg
mod 0 0 1 mem
* 1. The operand can be omitted. 2. The number of BCD digits is given by the CL register: a value between 1 and 254 can be set.
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg8 11110110 76543210 11100 reg 2 AWAL x reg8 AH = 0: CY0, V0 AH 0: CY1, V1 AWAL x (mem8) AH = 0: CY0, V0 AH 0: CY1, V1 DW, AWAW x reg16 DW = 0: CY0, V0 DW 0: CY1, V1 DW, AWAW x (mem16) DW = 0: CY0, V0 DW 0: CY1, V1 AWAL x reg8 AH = AL sign extension: CY0, V0 AH AL sign extension: CY1, V1 AWAL x (mem8) AH = AL sign extension: CY0, V0 AH AL sign extension: CY1, V1 DW, AWAW x reg16 DW = AW sign extension: CY0, V0 DW AW sign extension: CY1, V1 DW, AWAW x (mem16) DW = AW sign extension: CY0, V0 DW AW sign extension: CY1, V1 reg16reg16' x imm8 Product 16 bits: CY0, V0 Product > 16 bits: CY1, V1 reg16(mem16) x imm8 Product 16 bits: CY0, V0 Product > 16 bits: CY1, V1 reg16reg16' x imm16 Product 16 bits: CY0, V0 Product > 16 bits: CY1, V1 reg16(mem16) x imm16 Product 16 bits: CY0, V0 Product > 16 bits: CY1, V1 Bytes Operation
Flags AC CY V U x x P U S U Z U
mem8 MULU reg16
11110110
mod 1 0 0 mem
2 to 4
U
x
x
U
U
U
11110111
11100
reg
2
U
x
x
U
U
U
mem16 Multiplication instructions
11110111
mod 1 0 0 mem
2 to 4
U
x
x
U
U
U
reg8
11110110
11101
reg
2
U
x
x
U
U
U
mem8
11110110
mod 1 0 1 mem
2 to 4
U
x
x
U
U
U
reg16
11110111
11101
reg
2
U
x
x
U
U
U
mem16 MUL reg16, (reg16',)* imm8 reg16, mem16, imm8 reg16, (reg16',)* imm16 reg16, mem16, imm16
11110111
mod 1 0 1 mem
2 to 4
U
x
x
U
U
U
01101011
11
reg
reg'
3
U
x
x
U
U
U
01101011
mod reg
mem
3 to 5
U
x
x
U
U
U
01101001
11
reg
reg'
4
U
x
x
U
U
U
01101001
mod reg
mem
4 to 6
U
x
x
U
U
U
PD70433
*
The 2nd operand can be omitted, in which case the same register as the 1st operand is taken as being specified.
111
Instruction Group
Unsigned division instructions
112
Operation Code Mnemonic Operand(s) 76543210 76543210 tempAW If temp / reg8 FFH AHtemp%reg8, ALtemp / reg8 If temp / reg8 > FFH (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempAW If temp / (mem8) FFH AHtemp%(mem8), ALtemp / (mem8) If temp / (mem8) > FFH (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempDW, AW If temp / reg16 FFFFH DWtemp%reg16, AWtemp / reg16 If temp / reg16 > FFFFH (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempDW, AW If temp / (mem16) FFFFH DWtemp%(mem16), AWtemp / (mem16) If temp / (mem16) > FFFFH (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) Bytes Operation
Flags AC CY V P S Z
reg8
11110110
11110
reg
2
U
U
U
U
U
U
mem8
11110110
mod 1 1 0 mem
2 to 4
U
U
U
U
U
U
DIVU
reg16
11110111
11110
reg
2
U
U
U
U
U
U
mem16
11110111
mod 1 1 0 mem
2 to 4
U
U
U
U
U
U
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 76543210 tempAW If temp / reg8 > 0 and temp / reg8 7FH; or if temp / reg8 < 0 and temp / reg8 > 0 - 7FH - 1 AHtemp%reg8, ALtemp / reg8 If temp / reg8 > 0 and temp / reg8 > 7FH; or if temp / reg8 < 0 and temp / reg8 0 - 7FH - 1 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempAW If temp / (mem8) > 0 and temp / (mem8) 7FH; or if temp / (mem8) < 0 and temp / (mem8) > 0 - 7FH - 1 AHtemp%(mem8), ALtemp / (mem8) If temp / (mem8) > 0 and temp / (mem8) > 7FH; or if temp / (mem8) < 0 and temp / (mem8) 0 - 7FH - 1 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempDW, AW If temp / reg16 > 0 and temp / reg16 7FFFH; or if temp / reg16 < 0 and temp / reg16 > 0 - 7FFFH - 1 DWtemp%reg16, AWtemp / reg16 If temp / reg16 > 0 and temp / reg16 > 7FFFH; or if temp / reg16 < 0 and temp / reg16 0 - 7FFFH - 1 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) tempDW, AW If temp / (mem16) > 0 and temp / (mem16) 7FFFH; or if temp / (mem16) < 0 and temp / (mem16) > 0 - 7FFFH - 1 AHtemp%(mem16), AWtemp / (mem16) If temp / (mem16) > 0 and temp / (mem16) > 7FFFH; or if temp / (mem16) < 0 and temp / (mem16) 0 - 7FFFH - 1 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0, PS(3, 2), PC(1, 0) Bytes Operation
Flags AC CY V P S Z
reg8
11110110
11111
reg
2
U
U
U
U
U
U
Signed division instructions
mem8
11110110
mod 1 1 1 mem
2 to 4
U
U
U
U
U
U
DIV
reg16
11110111
11111
reg
2
U
U
U
U
U
U
mem16
11110111
mod 1 1 1 mem
2 to 4
U
U
U
U
U
U
PD70433
113
Instruction Group
BCD adjustment instructions
Data conversion instructions
Comparison instruction
114
Operation Code Mnemonic Operand(s) 76543210 ADJBA 00110111 76543210 1 If AL 0FH > 9 or AC = 1: ALAL + 6 AHAH + 1, AC1, CYAC, ALAL 0FH If AL 0FH > 9 or AC = 1: ALAL + 6, AC1 If AL > 9FH or CY = 1: ALAL + 60H, CY1 If AL 0FH > 9 or AC = 1: ALAL - 6, AC1 CYAC, ALAL 0FH If AL 0FH > 9 or AC = 1: ALAL - 6, CYCY AC, AC1 If AL > 9FH or CY = 1: ALAL - 60H, CY1 AHAH / 0AH, ALAL%0AH ALAH x 0AH + AL, AH0 If AL < 80H: AH0, otherwise: AHFFH If AW < 8000H: DW0, otherwise: DWFFFFH reg - reg' (mem)- reg reg - (mem) reg - imm (mem) - imm If W = 0, AL - imm If W = 1, AW - imm regreg (mem) - (mem) regreg + 1 (mem)(mem) + 1 x x x x x x x x x x x x x x x x Bytes Operation
Flags AC CY V x x U P U S U Z U
ADJ4A
00100111
1
x
x
U
x
x
x
ADJBS
00111111
1
x
x
U
U
U
U
ADJ4S
00101111
1
x
x
U
x x x
x x x
x x x
CVTBD CVTDB CVTBW CVTWL reg, reg' mem, reg reg, mem CMP reg, imm mem, imm acc, imm reg NOT mem
11010100 11010101 10011000 10011001 0 0 1 1 1 0 1W 0 0 1 1 1 0 0W 0 0 1 1 1 0 1W 1 0 0 0 0 0 sW 1 0 0 0 0 0 sW 0 0 1 1 1 1 0W 1 1 1 1 0 1 1W 1 1 1 1 0 1 1W 1 1 1 1 0 1 1W 1 1 1 1 0 1 1W
00001010 00001010
2 2 1 1
U U
U U
U U
11 mod mod
reg
reg'
2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3
x x x x x x
x x x x x x
x x x x x x
x x x x x x
reg mem reg mem reg
11111
mod 1 1 1 mem
11010
reg
2 2 to 4 2 2 to 4
mod 0 1 0 mem 11011 reg
*
reg NEG mem mod0 1 1mem
x x
x x
x x
x x
PD70433
* Complement operation instructions
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg, reg' mem, reg reg, mem TEST reg, imm mem, imm acc, imm reg, reg' mem, reg reg, mem AND reg, imm 1 0 0 0 0 0 0W 1 0 0 0 0 0 0W 0 1 0 0 1 0W 0 0 0 0 1 0 1W 0 0 0 0 1 0 0W 0 0 0 0 1 0 1W 1 0 0 0 0 0 0W 1 0 0 0 0 0 0W 0 0 0 0 1 1 0W 0 0 1 1 0 0 1W 0 0 1 1 0 0 0W 0 0 1 1 0 0 1W 1 0 0 0 0 0 0W 1 0 0 0 0 0 0W 0 0 1 1 0 1 0W 11 reg reg' mem mem reg 11 reg reg' mem mem reg 11100 reg 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 3 to 4 3 to 6 2 to 3 1 0 0 0 0 1 0W 1 0 0 0 0 1 0W 1 1 1 1 0 1 1W 1 1 1 1 0 1 1W 1 0 1 0 1 0 0W 0 0 1 0 0 0 1W 0 0 1 0 0 0 0W 0 0 1 0 0 0 1W 11 reg reg' mem mem 76543210 11 reg' reg mem reg 2 2 to 4 3 to 4 3 to 6 2 to 3 2 2 to 4 2 to 4 reg reg' (mem) reg reg imm (mem) imm If W = 0, AL imm8 If W = 1, AW imm16 regreg reg' (mem)(mem) reg regreg (mem) regreg imm (mem)(mem) imm If W = 0, ALAL imm8 If W = 1, AWAW imm16 regreg reg' (mem)(mem) reg regreg (mem) regreg imm (mem)(mem) imm If W = 0, ALAL imm8 If W = 1, AWAW imm16 regreg v reg' (mem)(mem) v reg' regreg v (mem) regreg v imm (mem)(mem) v imm If W = 0, ALAL v imm8 If W = 1, AWAW v imm16 Bytes Operation
Flags AC CY V U U U U U U U U U U U U U U U U U U U U U U U 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 P x x x x x x x x x x x x x x x x x x x x x x x S x x x x x x x x x x x x x x x x x x x x x x x Z x x x x x x x x x x x x x x x x x x x x x
mod reg 11000
mod 0 0 0 mem
mod reg mod reg
Logical operation instructions
mem, imm acc, imm reg, reg' mem, reg reg, mem OR reg, imm mem, imm acc, imm reg, reg' mem, reg reg, mem XOR reg, imm mem, imm acc, imm
mod 1 0 0 mem
mod reg mod reg 11001
mod 0 0 1 mem
mod reg mod reg 11110
PD70433
mod 1 1 0 mem
x x
115
Instruction Group
Bit manipulation instructions
116
Operation Code Mnemonic Operand(s) 76543210 reg8, CL mem8, CL reg16, CL mem16, CL TEST1 reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 reg8, CL mem8, CL reg16, CL mem16, CL NOT1 reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4 1110 1110 1111 1111 11000 reg 4 4 to 6 4 4 to 6 reg8 bit NO.imm3reg8 bit NO.imm3 (mem8) bit NO.imm3(mem8) bit NO.imm3 reg16 bit NO.imm4reg16 bit NO.imm4 (mem16) bit NO.imm4(mem16) bit NO.imm4 mod 0 0 0 mem 11000 reg 1000 1000 1001 1000 0110 0110 0111 0111 11000 reg 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 reg8 bit NO.imm3 = 0 : Z1 reg8 bit NO.imm3 = 1 : Z0 (mem8) bit NO.imm3 = 0 : Z1 (mem8) bit NO.imm3 = 1 : Z0 reg16 bit NO.imm4 = 0 : Z1 reg16 bit NO.imm4 = 1 : Z0 (mem16) bit NO.imm4 = 0 : Z1 (mem16) bit NO.imm4 = 1 : Z0 reg8 bit NO.CLreg8 bit NO.CL (mem8) bit NO.CL(mem8) bit NO.CL reg16 bit NO.CLreg16 bit NO.CL (mem16) bit NO.CL(mem16) bit NO.CL U U U U 0 0 0 0 00010000 0000 0001 0001 76543210 11000 reg 3 3 to 5 3 3 to 5 reg8 bit NO.CL = 0 : Z1 reg8 bit NO.CL = 1 : Z0 (mem)8 bit NO.CL = 0 : Z1 (mem)8 bit NO.CL = 1 : Z0 reg16 bit NO.CL = 0 : Z1 reg16 bit NO.CL = 1 : Z0 (mem16) bit NO.CL = 0 : Z1 (mem16) bit NO.CL = 1 : Z0 Bytes Operation
Flags AC CY V U U U U 0 0 0 0 0 0 0 0 0 0 0 0 P U U U U U U U U S U U U U U U U U Z x x x x x x x x
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem
mod 0 0 0 mem
2nd byte *
3rd byte *
*
1
1st byte = 0FH
CYCY x
NOT1
CY
11110101
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg8, CL mem8, CL reg16, CL mem16, CL CLR1 reg8, imm3 1010 1010 1011 1011 0100 0100 0101 0101 1100 1100 1101 1101 11000 reg 4 4 to 6 4 4 to 6 3 3 to 5 3 3 to 5 4 4 to 6 4 4 to 6 reg8 bit NO.imm30 (mem8) bit NO.imm30 reg16 bi NO.imm40 (mem16) bit NO.imm40 reg8 bit NO.CL1 (mem8) bit NO.CL1 reg16 bit NO.CL1 (mem16) bit NO.CL1 reg8 bit NO.imm31 (mem8) bit NO.imm31 reg16 bi NO.imm41 (mem16) bit NO.imm41 00010010 0010 0011 0011 76543210 11000 reg 3 3 to 5 3 3 to 5 reg8 bit NO.CL0 (mem8) bit NO.CL0 reg16 bit NO.CL0 (mem16) bit NO.CL0 Bytes Operation
Flags AC CY V P S Z
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem
Bit manipulation instructions
mem8, imm3 reg16, imm4 mem16, imm4 reg8, CL mem8, CL reg16, CL mem16, CL SET1 reg8, imm3 mem8, imm3 reg16, imm4 mem16, imm4
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem 11000 reg
mod 0 0 0 mem
2nd byte * CY CLR1 DIR CY SET1 DIR 11111101 11111100 11111001 11111000
3rd byte *
*
1 1 1 1
1st byte = 0FH
CY0 DIR0 CY1 DIR0 1 0
PD70433
117
Instruction Group
Bit manipulation instruction
Queue manipulation instructions
118
*
Operation Code Mnemonic Operand(s) 76543210 00001111 reg8 11000 mem8 mod 0 0 0 mem BSCH* 00001111 reg16 11000 mem16 mod 0 0 0 mem QHOUT QOUT* QTIN* * imm16 imm16 imm16 00001111 00001111 00001111 01110000 01110001 01110010 reg 00111101 00001111 00111101 reg 00111100 00001111 76543210 00111100 3
<1> CL 0 <2> [When reg8 bit No.CL=0] if CL<7, re-executed from CL CL+1, <2> if CL=7 Z 1 Z 0
Flags Bytes Operation AC CY V U U U P U S U Z x
[When reg8 bit No.CL=1] <1> CL 0 <2> [When mem8 bit No.CL=0] if CL<7, re-executed from CL CL+1, <2> 3 to 5 U if CL=7 Z 1 [When mem8 bit No.CL=1] Z 0 <1> CL 0 <2> [When reg16 bit No.CL=0] if CL<15, re-executed from CL CL+1, <2> 3 U if CL=15 Z 1 [When reg16 bit No.CL=1] Z 0 <1> CL 0 <2> [When mem16 bit No.CL=0] if CL<15, re-executed from CL CL+1, <2> 3 to 5 U if CL=15 Z 1 [When mem16 bit No.CL=1] Z 0
U
U
U
U
x
U
U
U
U
x
U
U
U
U
x x x
4 4 4
Removes block queued at head of queue and stores its segment address in P2. Removes queue block indicated by P2. Queues block indicated by P2 at end of queue.
U U
U U
U U
U U
U U
This instruction is newly added to the V25 or V35. P2: Parameter table (in register file)
Remarks
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 reg, 1 1 1 0 1 0 0 0W 76543210 11100 reg 2 CYreg MSB, regreg x 2 If reg MSB CY, V1 If reg MSB = CY, V0 CY(mem) MSB, (mem)(mem) x 2 If (mem) MSB CY, V1 If (mem) MSB = CY, V0 tempCL, while temp 0, the following operations are repeated: CYreg MSB, regreg x 2 temptemp - 1 tempCL, while temp 0, the following operations are repeated: CY(mem) MSB, (mem)(mem) x 2 temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CYreg MSB, regreg x 2 temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CY(mem) MSB, (mem)(mem) x 2 temptemp - 1 CYreg LSB, regreg / 2 If reg MSB bit after reg MSB: V1 If reg MSB = bit after reg MSB: V0 CY(mem) LSB, (mem)(mem) / 2 If (mem) MSB bit after (mem) MSB: V1 If (mem) MSB = bit after (mem) MSB: V0 tempCL, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 temptemp - 1 tempCL, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 temptemp - 1 Bytes Operation
Flags AC CY V U x x P x S x Z x
mem, 1
1 1 0 1 0 0 0W
mod 1 0 0 mem
2 to 4
U
x
x
x
x
x
reg, CL SHL mem, CL
1 1 0 1 0 0 1W
11100
reg
2
U
x
U
x
x
x
1 1 0 1 0 0 1W
mod 1 0 0 mem
2 to 4
U
x
U
x
x
x
reg, imm8 Shift instructions
1 1 0 0 0 0 0W
11100
reg
3
U
x
U
x
x
x
mem, imm8
1 1 0 0 0 0 0W
mod 1 0 0 mem
3 to 5
U
x
U
x
x
x
reg, 1
1 1 0 1 0 0 0W
11101
reg
2
U
x
x
x
x
x
mem, 1
1 1 0 1 0 0 0W
mod 1 0 1 mem
2 to 4
U
x
x
x
x
x
reg, CL SHR mem, CL
1 1 0 1 0 0 1W
11101
reg
2
U
x
U
x
x
x
1 1 0 1 0 0 1W
mod 1 0 1 mem
2 to 4
U
x
U
x
x
x
reg, imm8
1 1 0 0 0 0 0W
11101
reg
3
U
x
U
x
x
x
mem, imm8
1 1 0 0 0 0 0W
mod 1 0 1 mem
3 to 5
U
x
U
x
x
x
PD70433
119
Instruction Group
Shift instruction
Rotate instruction
120
Operation Code Mnemonic Operand(s) 76543210 reg, 1 mem, 1 1 1 0 1 0 0 0W 1 1 0 1 0 0 0W 76543210 11111 reg 2 2 to 4 CYreg LSB, regreg / 2, V0 MSB of operand is unchanged. CY(mem) LSB, (mem)(mem) / 2, V0 MSB of operand is unchanged. tempCL, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 temptemp - 1, MSB of operand is unchanged. tempCL, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 temptemp - 1, MSB of operand is unchanged. tempimm8, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 temptemp - 1, MSB of operand is unchanged. tempimm8, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 temptemp - 1, MSB of operand is unchanged. CYreg MSB, regreg x 2 + CY reg MSB CY: V1 reg MSB = CY: V0 CY(mem) MSB, (mem)(mem) x 2 + CY (mem) MSB CY: V1 (mem) MSB = CY: V0 tempCL, while temp 0, the following instructions are repeated: CYreg MSB, regreg x 2 + CY temptemp - 1 tempCL, while temp 0, the following instructions are repeated: CY(mem) MSB, (mem)(mem) x 2 + CY temptemp - 1 tempimm8, while temp 0, the following instructions are repeated: CYreg MSB, regreg x 2 + CY temptemp - 1 tempimm8, while temp 0, the following instructions are repeated: CY(mem) MSB, (mem)(mem) x 2 + CY temptemp - 1 Bytes Operation
Flags AC CY V U U x x x 0 0 P x x x S x x x Z x x x
mod 1 1 1 mem
reg, CL SHRA mem, CL
1 1 0 1 0 0 1W
11111
reg
2
U
U
1 1 0 1 0 0 1W
mod 1 1 1 mem
2 to 4
U
x
U
x
x
x
reg, imm8
1 1 0 0 0 0 0W
11111
reg
3
U
x
U
x
x
x
mem, imm8
1 1 0 0 0 0 0W
mod 1 1 1 mem
3 to 5
U
x
U
x
x
x
reg, 1
1 1 0 1 0 0 0W
11000
reg
2
x
x
mem, 1
1 1 0 1 0 0 0W
mod 0 0 0 mem
2 to 4
x
x
reg, CL ROL mem, CL
1 1 0 1 0 0 1W
11000
reg
2
x
U
1 1 0 1 0 0 1W
mod 0 0 0 mem
2 to 4
x
U
reg, imm8
1 1 0 0 0 0 0W
11000
reg
3
x
U
mem, imm8
1 1 0 0 0 0 0W
mod 0 0 0 mem
3 to 5
x
U
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 76543210 CYreg LSB, regreg / 2 reg MSBCY reg MSB bit after reg MSB: V1 reg MSB = bit after reg MSB: V0 CY(mem) LSB, (mem)(mem) / 2 (mem) MSBCY (mem) MSB bit after (mem) MSB: V1 (mem) MSB = bit after (mem) MSB: V0 tempCL, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 reg MSBCY temptemp - 1 tempCL, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 (mem) MSBCY temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CYreg LSB, regreg / 2 reg MSBCY temptemp - 1 tempimm8, while temp 0, the following operations are repeated: CY(mem) LSB, (mem)(mem) / 2 (mem) MSBCY temptemp - 1 tmpcyCY, CYreg MSB regreg x 2 + tmpcy reg MSB CY: V1 reg MSB = CY: V0 tmpcyCY, CY(mem) MSB (mem)(mem) x 2 + tmpcy (mem) MSB CY: V1 (mem) MSB = CY: V0 tempCL, while temp 0, the following operations are repeated: tmpcyCY, CYreg MSB regreg x 2 + tmpcy temptemp - 1 tempCL, while temp 0, the following operations are repeated: tmpcyCY, CY(mem) MSB (mem)(mem) x 2 + tmpcy temptemp - 1 Bytes Operation
Flags AC CY V x x P S Z
reg, 1
1 1 0 1 0 0 0W
11001
reg
2
mem, 1
1 1 0 1 0 0 0W
mod 0 0 1 mem
2 to 4
x
x
reg, CL ROR mem, CL
1 1 0 1 0 0 1W
11001
reg
2
x
U
1 1 0 1 0 0 1W
mod 0 0 1 mem
2 to 4
x
U
Rotate instructions
reg, imm8
1 1 0 0 0 0 0W
11001
reg
3
x
U
mem, imm8
1 1 0 0 0 0 0W
mod 0 0 1 mem
3 to 5
x
U
reg, 1
1 1 0 1 0 0 0W
11010
reg
2
x
x
mem, 1 ROLC reg, CL
1 1 0 1 0 0 0W
mod 0 1 0 mem
2 to 4
x
x
1 1 0 1 0 0 1W
11010
reg
2
x
U
PD70433
mem, CL
1 1 0 1 0 0 1W
mod 0 1 0 mem
2 to 4
x
U
121
Instruction Group
Rotate instructions
122
Operation Code Mnemonic Operand(s) 76543210 76543210 tempimm8, while temp 0, the following instructions are repeated: tmpcyCY, CYreg MSB regreg x 2 + tmpcy temptemp - 1 tempimm8, while temp 0, the following instructions are repeated: tmpcyCY, CY(mem) MSB (mem)(mem) x 2 + tmpcy temptemp - 1 tmpcyCY, CYreg LSB regreg / 2 reg MSBtmpcy reg MSB bit after reg MSB: V1 reg MSB = bit after reg MSB: V0 tmpcyCY, CY(mem) LSB (mem)(mem) / 2 (mem) MSBtmpcy (mem) MSB bit after (mem) MSB: V1 (mem) MSB = bit after (mem) MSB: V0 tempCL, while temp 0, the following operations are repeated: tmpcyCY, CYreg LSB regreg / 2 reg MSBtmpcy temptemp - 1 tempCL, while temp 0, the following operations are repeated: tmpcyCY, CY(mem) LSB (mem)(mem) / 2 (mem) MSBtmpcy temptemp - 1 tempimm8, while temp 0, the following operations are repeated: tmpcyCY, CYreg LSB regreg / 2 reg MSBtmpcy temptemp - 1 tempimm8, while temp 0, the following operations are repeated: tmpcyCY, CY(mem) LSB (mem)(mem) / 2 (mem) MSBtmpcy temptemp - 1 Bytes Operation
Flags AC CY V x P S Z
reg, imm8 ROLC mem, imm8
1 1 0 0 0 0 0W
11010
reg
3
U
1 1 0 0 0 0 0W
mod 0 1 0 mem
3 to 5
x
U
reg, 1
1 1 0 1 0 0 0W
11011
reg
2
x
x
mem, 1
1 1 0 1 0 0 0W
mod 0 1 1 mem
2 to 4
x
x
reg, CL RORC mem, CL
1 1 0 1 0 0 1W
11011
reg
2
x
U
1 1 0 1 0 0 1W
mod 0 1 1 mem
2 to 4
x
U
reg, imm8
1 1 0 0 0 0 0W
11011
reg
3
x
U
mem, imm8
1 1 0 0 0 0 0W
mod 0 1 1 mem
3 to 5
x
U
PD70433
Instruction Group
Operation Code Mnemonic Operand(s) 76543210 near-proc regptr16 CALL memptr16 11101000 11111111 11111111 11010 reg 76543210 3 2 2 to 4 (SP - 1, SP - 2)PC, SPSP - 2 PCPC + disp (SP - 1, SP - 2)PC, SPregptr16 SPSP - 2 (SP - 1, SP - 2)PC, SPSP - 2 PC(memptr16) (SP - 1, SP - 2)PS, (SP - 3, SP - 4)PC SPSP - 4 PCseg, PCoffset (SP - 1, SP - 2)PS, (SP - 3, SP - 4)PC SPSP - 4 PC(memptr32 + 2), PC(memptr32) PC(SP + 1, SP) SPSP + 2 PC(SP + 1, SP) SPSP + 2, SPSP + pop-value PC(SP + 1, SP) PS(SP + 3, SP + 2) SPSP + 4 PC(SP + 1, SP) PS(SP + 3, SP + 2) SPSP + 4, SPSP + pop-value (SP - 1, SP - 2)(mem16) SPSP - 2 (SP - 1, SP - 2)reg16 SPSP - 2 (SP - 1, SP - 2)sreg SPSP - 2 (SP - 1, SP - 2)PSW SPSP - 2 Push registers on the stack (SP - 1, SP - 2)imm8 sign extension SPSP - 2 (SP - 1, SP - 2)imm16 SPSP - 2 (SP - 1, SP - 2)DS2 SPSP - 2 Bytes Operation
Flags AC CY V P S Z
mod 0 1 0 mem
Subroutine control instructions
far-proc
10011010
5
memptr32
11111111
mod 0 1 1 mem
2 to 4
11000011 pop-value RET 11001011 11000010
1 3
1
pop-value
11001010
3
mem16 reg16 Stack manipulation instruction sreg PSW R imm8 imm16 DS2 *
11111111 01010 reg
mod 1 1 0 mem
2 to 4 1 1 1 1 2 3
0 0 0 sreg 1 1 0 10011100 01100000 01101010 01101000 00001111 00111110
PUSH
PD70433
2
123
*
This instruction is newly added to the V25 or V35.
Instruction Group
Stack manipulation instructions
Branch instruction
124
Operation Code Mnemonic Operand(s) 76543210 PUSH DS3/VPC* mem16 reg16 sreg POP PSW R DS2* DS3/VPC PREPARE DISPOSE near-label short-label regptr16 BR memptr16 far-label memptr32 * 00001111 10001111 01011 reg 76543210 00110110 mod 0 0 0 mem 2 2 to 4 1 1 1 1 00111111 00110111 2 2 4 1 3 2 11100 reg 2 2 to 4 5 mod 1 0 1 mem 2 to 4 (SP - 1, SP - 2)DS3/VPC SPSP - 2 SPSP + 2 (mem16)(SP - 1, SP - 2) SPSP + 2 reg16(SP - 1, SP - 2) SPSP + 2 sreg16(SP - 1, SP - 2) SPSP + 2 PSW(SP - 1, SP - 2) Pop registers from the stack SPSP + 2 DS2(SP - 1, SP - 2) SPSP + 2 DS3/VPC(SP - 1, SP - 2) Prepare New Stack Frame Dispose of Stack Frame PCPC + disp PCPC + ext-disp8 PCregptr16 PC(memptr16) PSseg PCoffset PS(memptr32 + 2) PC(memptr32) sreg : SS, DS0, DS1 R R Bytes Operation
Flags AC CY V P S Z
0 0 0 sreg 1 1 1 10011101 01100001 00001111 00001111 11001000 11001001 11101001 11101011 11111111 11111111 11101010 11111111
R
R
R
R
imm16, imm8
mod 1 0 0 mem
*
This instruction is newly added to the V25 or V35.
PD70433
Instruction Group
Operation Code Mnemonic BV BNV BC BL BNC BNL BE BZ BNE BNZ BNH BH Operand(s) 76543210 short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label short-label sfr, imm3, short-label sfrl, imm3, short-label 01110000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 11100000 0001 0010 0011 00001111 00001111 10011100 10011101 76543210 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 5 5 if V = 1 if V = 0 if CY = 1 if CY = 0 if Z = 1 if Z = 0 if CY Z = 1 if CY Z = 0 if S = 1 if S = 0 if P = 1 if P = 0 if S V = 1 if S V = 0 if (S Z) Z = 1 if (S V) Z = 0 CW = CW - 1 if Z = 0 and CW 0 CW = CW - 1 if Z = 1 and CW 0 CW = CW - 1 if CW 0 if CW = 0 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 PCPC + ext-disp8 Bytes Operation
Flags AC CY V P S Z
Conditional branch instructions
BN BP BPE BPO BLT BGE BLE BGT DBNZNE DBNZE DBNZ BCWZ BTCLR*1 BTCLRL*2
PD70433
If (sfr) bit No. imm3 = 1: PCPC + ext-disp8, (sfr) bit No.imm30 If (sfrl) bit No. imm3 = 1: PCPC + ext-disp8, (sfrl) bit No.imm30
125
* 1. This instruction is newly added to the V20 or V30. 2. This instruction is newly added to the V25 or V35.
Instruction Group
Interrupt instructions
Register bank switching instructions
Dedicated fax instructions
126
Operation Code Mnemonic Operand(s) 76543210 76543210 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0 PS(15, 14), PC(13, 12) (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0 PS(n x 4 + 3, n x 4 + 2), PC(n x 4 + 1, n x 4) n = imm8 If V = 1: (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0 PS(19, 18), PC(17, 16) PC(SP + 1, SP), PS(SP + 3, SP + 2) PSW(SP + 5, SP + 4), SPSP + 6 PCValue of PC save area in currently selected bank register, PSWValue of PSW save area in currently selected bank register Indicates to interrupt controller incorporated in CPU that interrupt servicing has ended. If (mem32) > reg16 or (mem32 + 2) < reg16 (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC, SPSP - 6 IE0, BRK0 PS(23, 22), PC(21, 20) tempPSW RB3 to 0reg16 low-order 4 bits, IE0, BRK0 PSW save area in newly selected register banktemp PC save area in newly selected register bankPC PSW save area in currently selected register bankPSW PC save area in currently selected register bankPC RB3-0reg16 low-order 4 bits PSWValue of PSW save area in newly selected register bank PCValue of PC save area in newly selected register bank If CH + CL 16: BW, DWDS1:IY output to transmit buffer If CH + CL < 16: CH + CL CH, BW, DWBW Part exceeding 16 bits: CH+CL-16CH, BW, DWBW Stores 1 line pixel data change point information in change point table (start white run length). Generates MH code from change point table. Generates MR code from change point table. U U x x R R R R Bytes Operation
Flags AC CY V P S Z
3 BRK imm8 ( 3)
11001100
1
11001101
2
BRKV
11001110
1
RETI RETRBI*
11001111 00001111 10010001
1 2
R R
R R
R R
R R
FINT*
00001111
10010010
2
CHKIND
reg, mem32
01100010
mod reg mem
2 to 4
00001111 BRKCS* reg16 11000 reg
00101101 3
00001111 TSKSW* reg16 11111 reg
10010100 3
x
x
x
x
x
x
ALBIT
00001111
10011010
2
U
x
U
U
U
x
PD70433
COLTRP MHENC MRENC
00001111 00001111 00001111
10011011 10010011 10010111
2 2 2
U U
U U
U U
x x
*
This instruction is newly added to the V20 or V30.
Instruction Group
Operation Code Mnemonic SCHEOL GETBIT MHDEC MRDEC CNVTRP HALT STOP*1 POLL Operand(s) 76543210 00001111 00001111 00001111 00001111 00001111 11110100 00001111 10011011 11111010 11111011 11110000 fp-op FPO1 fp-op, mem fp-op FPO2 fp-op, mem NOP 0110011X 10010000 0000 1 1 1 1 1 0 0 1 0 110 4 imm8 *4 DS2: *2 DS3: *2 0 0 1 sreg 1 1 0 01100011 11010110 11110001 imm8 1 1 1 1 mod Y Y Y mem 2 to 4 1 PC(01DH; 01CH), PS(01FH, 01EH) No Operation
When imm8 = imm8' WDM registerimm8 When imm8 imm8' (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC - x*6, SPSP - 6 IE0, BRK0 PC(20H, 21H), PS(22H, 23H)
Flags Bytes Operation AC CY V 2 2 2 2 2 1 "EOL" detection in MH/MR code Fetches pixel data start bit and sets it to CY flag. Generates change point table from MH code. Generates change point table from MR code. Converts 1 line change point information in change point table to pixel data. CPU Halt CPU Stop Poll and wait IE0 IE1 Bus Lock Prefix (SP - 1, SP - 2)PSW, (SP - 3, SP - 4)PS (SP - 5, SP - 6)PC - x*6, SPSP - 6 IE0, BRK0 U U U U x x x x U U U U P U U U U S U U U U Z x x x x
76543210 01111000 01111001 01111100 01111101 01111010
Dedicated fax instructions
10011110
2 1 1 1 1
CPU control instructions
DI EI BUSLOCK
11011XXX 11011XXX 0110011X
1 1YYYZZZ mod Y Y Y mem 1 1YYYZZZ
2 2 to 4 2
*3
RSTWDT*2
imm8, imm8
Segment override prefix Extended segment override prefix Extended segment override prefix Register file override prefix
*5
IRAM: *2
PD70433
* 1. This instruction is newly added to the V20 or V30. 2. This instruction is newly added to the V25 or V35. 3. Watchdog timer manipulation instruction 4. Four kinds: DS0:, DS1:, PS:, SS: 5. Register file space access override prefix instruction 6. x: Number of instruction bytes + number of prefixes
127
PD70433
18. ELECTRICAL SPECIFICATIONS
This section shows the electrical specifications of the V55PITM using the three categories below. PD70433GD/R/GJ-12: PD70433-12 PD70433GD/R/GJ-16: PD70433-16 ABSOLUTE MAXIMUM RATINGS (TA = 25 C)
PARAMETER SYMBOL VDD AVDD Supply voltage AVSS AVREF Input voltage Output voltage Output current low VI VO One pin IOL Total of all pins One pin Output current high Operating ambient temperature Storage temperature IOH Total of all pins TA Tstg -20 -40 to +85 -65 to +150 mA C C 100 -1.0 mA mA -0.5 to +0.5 -0.5 to AVDD + 0.3 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 4.0 V V V V mA TEST CONDITIONS RATINGS -0.5 to +7.0 -0.5 to VDD + 0.5 UNIT V V
Notes 1. The IC product output (or input/output) pins should not be directly connected between VDD, VCC or GND. However, direct connection between the open-drain pins or betwen the open collector pins is possible. Direct connection is also possible for an external circuit via timing design that avoids collision of output at pins which become high impedance. 2. Exceeding the absolute maximum ratings even in one of the parameters even for an instant may affect the product quality. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore avoid using the product close to the rated values. The specifications and conditions shown in the DC characteristics and AC characteristics comprise the normal operation and guaranteed quality range.
128
PD70433
DC Characteristics (TA = -40 to +85 C, VDD = +5.0 V 10 %)
PARAMETER Input voltage low
SYMBOL VIL1 VIL2 *1 *2 *1 *2
TEST CONDITIONS
MIN. 0 0 2.2 0.8VDD
TYP.
MAX. 0.8 0.2VDD VDD VDD
UNIT V V V V V V V
Input voltage high
VIH1 VIH2
Schmitt-triggered input threshold voltage
VT VT
+
*3, rise *3, fall
-
3.3 1.6 0.5 0.45 VDD -1.0 10 10 5.4fX + 30 5.4fX + 50 3.7 fX 10 1.5 0.6 10 3.7fX + 20 50 2.5 1 50
-
Schmitt-triggered input hysteresis width Output voltage low Output voltage high Input leakage current Output leakage current VDD supply current*4
VT - VT VOL VOH ILI ILO IDD1 IDD2 IDD3
+
*3 IOL = 2.0 mA IOH = -0.4 mA 0 V VI VDD 0 V VO VDD Operating mode HALT mode STOP mode Operating mode HALT mode STOP mode
V V
A A
mA mA
A
mA mA
AVDD supply current
AIDD1 AIDD2 AIDD3
A
* 1. Other than *2 2. RESET, P10/NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RxD0/SB1/SI0, P32/TxC/SCK0, P33/CTS0, P35/RxD1/SI1, P36/SCK1/CTS1 3. RESET, P10/NMI, P11/INTP0 to P16/INTP5 4. The unit for the constants 5.4 and 3.7 is mA/MHz.
CAPACITANCE (TA = 25 C, VDD = 0 V)
PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CI CO CIO TEST CONDITIONS fC = 1 MHz Unmeasured pins are returned to 0 V. MIN. TYP. MAX. 10 20 20 UNIT pF pF pF
OPERATING CONDITIONS
PART NUMBER INT. CLOCK FREQUENCY 0.25 MHz fX 12.5 MHz 0.25 MHz fX 12.5 MHz OPERATING TEMPERATURE (TA) -40 to +85 C SUPPLY VOLTAGE (VDD) +5.0 V 10 %
PD70433-12 PD70433-16
129
PD70433
RECOMMENDED OSCILLATION CIRCUIT The circuit shown below is recommended for a clock input. (1) Ceramic resonator connection (TA = -40 to +85 C 10 %, VDD = 5 V 10 %)
X1
X2
C1
C2
MANUFACTURER Murata Mfg. Co., Ltd.
OSCILLATOR FREQUENCY fXX [MHz] 25 32
RECOMMENDED CONSTANTS PRODUCT NAME C1 [pF] CSA25.00MXZ040 CSA32.00MXZ040 5 3 C2 [pF] 5 3
Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the PD70433 with a resonator, careful evaluation is required.
(2) Crystal resonator connection (a) Basic-wave recommended condition (TA = -10 to +70 C, V
DD
= 5 V 10 %)
X1 R C1
X2
C2
MANUFACTURER Kinseki
OSCILLATOR FREQUENCY fXX [MHz] 25
RECOMMENDED CONSTANTS PRODUCT NAME C1 [pF] HC-49/U-S 5 10 C2 [pF] 5 10 R [] 200 -
Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the PD70433 with a resonator, careful evaluation is required.
130
PD70433
= 5 V 10 %)
(b) 3rd-overtone recommended condition (TA = -20 to +70 C, V
DD
X1 C3 R
X2
C1
L
C2
MANUFACTURER Kinseki
OSCILLATOR FREQUENCY fXX [MHz] 25 32
RECOMMENDED CONSTANTS PRODUCT NAME C1 [pF] HC-49/U 15 10 C2 [pF] 15 5 C3 [pF] 1000 1000 L [H] 3.3 3.3 R [] 100 100
Notes 1. The oscillator should be located as close to the X1 and X2 pins as possible. 2. Other signal lines should not cross the dotted area. 3. When matching the PD70433 with a resonator, careful evaluation is required.
(3) External clock input
X1
X2 Open
131
PD70433
AC CHARACTERISTICS (TA = -40 to +85 C, VDD = +5.0 V 10 %) (1) PD70433-12
PARAMETER X1 input cycle time X1 input high-level width X1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle time CLKOUT output high-level width CLKOUT output low-level width CLKOUT output rise time CLKOUT output fall time Input rise time 12 13 Input fall time 14 Output rise time Output fall time CLKOUT delay time from X1 Address delay time from CLKOUT Address hold time (from CLKOUT) 19 Address float delay time from CLKOUT Address setup time (to ASTB) Address hold time (from ASTB) ASTB delay time from CLKOUT ASTB delay time from CLKOUT ASTB high-level width RD delay time from CLKOUT RD delay time from CLKOUT RD low-level width RD delay time from address float Address delay time from RD 20 21 22 23 24 25 26 27 28 29 30 tHKA2 tFKA tSAST tHSTA tDKSTL tDKSTH tWSTH tDKRL tDKRH tWRL tFARL tDRA 0 tHKA1 (n + 0.5)T - 25 0.5T - 15 0 0 (n + 1)T - 15 0 0 (N + 1.5)T - 15 0 0.5T 22 22 22 22 36 ns ns ns ns ns ns ns ns ns ns ns ns 15 16 118 17 18 tIF2 tOR tOF tDXK tDKA tHKA1 X2: open 5 0 *2 20 10 10 18 27 ns ns ns ns ns ns tIR2 tIF1 *2 *1 20 10 ns ns SYMBOL 1 2 3 4 5 6 7 8 9 10 11 tCYX tWXH tWXL tXR tXF tCYK tWKH tWKL tKR tKF tIR1 *1 80 0.5T - 5 0.5T - 5 7 7 10 TEST CONDITIONS MIN. 40 15 15 10 10 4000 MAX. 250 UNIT ns ns ns ns ns ns ns ns ns ns ns
n : Number of address wait states N : Number of data wait states T : tCYK * 1. Other than *2 2. RESET, P10 NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RXD0/SB1/SI0, P32/TXC/SCK0, P33/ CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 Remark Numbers in the Symbol column correspond to numbers in the timing charts.
132
PD70433
PARAMETER ASTB delay time from RD, IORD
RD, IORD delay time from WRL, WRH, IOWR
SYMBOL 119 120 31 32 33 34 35 36 37 38 39 40 41 42 43 121 122 44 45 46 47 48 tDRSTH tDWRH tDKDX tHKDX tSDK tHKDR tDKWL tDKWH tWWL tDKD tHKDW tDWSTH tDKRAL tDKRAH tWRAH tDWRAH tSARAL tSRYHK tHKRYL tSRYLK tHKRYH tWRSL1 tWRSL2 tWNIH tWNIL tSIQK tWIQH tWIQL tSPLK tSHQK tDKHA tFCHA tDHAC
TEST CONDITIONS
MIN. 0 0 0 0 11 0 0 0 (N + 1)T - 12 3 0 0 nT 0 (n + 1)T - 15 (N + 0.5)T - 10 nT - 12 18 12 18 12
MAX.
UNIT ns ns
DEX delay time from CLKOUT DEX hold time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) WR delay time from CLKOUT WR delay time from CLKOUT WR low-level width Data output delay time from CLKOUT Data output hold time (from CLKOUT) ASTB delay time from WR RAS delay time from CLKOUT RAS delay time from CLKOUT RAS high-level width RAS delay time from WRH, WRL Address setup time (to RAS) READY setup time (to CLKOUT) READY hold time (from CLKOUT) READY setup time (to CLKOUT) READY hold time (from CLKOUT) RESET low-level width
27
ns ns ns ns
22 22
ns ns ns
27
ns ns ns
nT + 22 22
ns ns ns ns ns ns ns ns ns ms ns
STOP release/power-on reset System reset
30 1000 + 2T 5 5
49 NMI high-level width NMI low-level width INTPm setup time (to CLKOUT) INTPm high-level width INTPm low-level width POLL setup time (to CLKOUT) HLDRQ setup time (to CLKOUT) HLDAK delay time from CLKOUT HLDAK delay time from bus float Bus output delay time from HLDAK 50 51 52 53 54 55 56 57 58 59
s s
ns ns ns ns ns 27 ns ns ns
m = 0 to 5 m = 0 to 5 m = 0 to 5
25 10T 10T 25 25 0 0 T - 22.5
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
133
PD70433
PARAMETER HLDAK delay time from HLDRQ Bus output delay time from HLDRQ HLDRQ low-level width HLDAK low-level width BUSLOCK delay time from CLKOUT DMARQm setup time (to CLKOUT) DMARQm high-level width DMARQm low-level width DMARQm setup time (to CLKOUT) DMARQm low-level hold time (from CLKOUT) DMAAKm delay time from CLKOUT DMAAKm low-level width TCEm delay time from CLKOUT TCEm low-level width TOUT high-level width TOUT low-level width WDTOUT low-level width SCK cycle time
SYMBOL 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 tDHQHA tDHQC tWHQL tWHAL tDKBL tSDQK tWDQH tWDQL tSKDQ tHKDQ tDKDA tWDAL tDKTE tWTCL tWTOH tWTOL tWWTL
TEST CONDITIONS
MIN. 0.5T - 15 0.5T + 45 2T 3T - 10 0
MAX. 3.5T + 35
UNIT ns ns ns ns
27
ns ns ns ns
Except demand release mode; m = 0, 1 Except demand release mode; m = 0, 1 Except demand release mode; m = 0, 1 Demand release mode; m = 0 or 1 Demand release mode; m = 0 or 1 m = 0 or 1 m = 0 or 1 m = 0 or 1 m = 0 or 1
25 2T 2T 5 12 0 (3 + n + N)T - 10 0 T - 10 8T - 10 8T - 10 32T - 10 27 27
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Input tCYSK Output Input SCK high-level width 78 tWSKH Output Input SCK low-level width SI, SB setup time (to SCK) SI, SB hold time (from SCK) 79 80 81 82 SO, SB delay time from SCK 83 SB high-level hold time (from SCK) SB low-level setup time (to SCK) SB high-level width SB low-level width 84 85 86 87 tDSKSB2 tHSKSB SBI mode tSSBSK tWSBH tWSBL SBI mode (open-drain output, RL = 1 k) tWSKL Output tSSSK tHSKS tDSKSB1 IOE mode (CMOS push-pull output)
8T 8T - 10 4T - 10 4T - 10 4T - 10 4T - 10 50 150 0 0 4T 4T 4T 4T 90 190
ns ns ns ns ns ns
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
134
PD70433
PARAMETER CTS high-level width CTS low-level width Transmit/receive data cycle TXC output clock cycle TXC output clock high-level width TXC output clock low-level width TXD delay time from TXC TXD delay time from CTS DATASTB setup time DATASTB low-level width
SYMBOL 88 89 90 91 92 93 94 95 96 97 98 tWCTH tWCTL tCYD tCYC tWCH tWCL tDTCTD tDCTTD tSDSK tWDSL1 tWDSL2 tSPDDS1 tHDSPD1 tDDSBY1 tSPDDS2 tHDSPD2 tDDSBY2 tDPDDSL tSDSAK tWAKL tSDSBY tWBYH tDKP tSPK tHKP tHSTDQ tDKREL tDKREH tDRERA tDSTLRL
TEST CONDITIONS
MIN. 2T 2T
MAX.
UNIT ns ns ns ns ns ns
UART
32T 32T 16T - 10
UART
16T - 10 0 90 2tCYC
ns ns ns ns
Input mode Input mode Output mode Input mode (DATASTB latch mode)
25 2T 2T - 10 45 4T 4T 512T
ns ns ns ns ns ns
PD setup time (to DATASTB) PD hold time (from DATASTB) BUSY delay time from DATASTB PD setup time (to DATASTB) PD hold time (from DATASTB) BUSY delay time from DATASTB DATASTB delay time from PD DATASTB setup time (to ACK) ACK input low-level width DATASTB setup time (to BUSY) BUSY input high-level width Port output delay time (from CLKOUT) Port input setup time (to CLKOUT) Port input hold time (from CLKOUT) DMARQm high-level hold time (from ASTB) REFRQ delay time from CLKOUT REFRQ delay time from CLKOUT RAS delay time from REFRQ RD delay time from ASTB
99 100 101 102 103 104 105 106 107 108 109 123 124 125 126 127 128 129 130
Input mode (DATASTB latch mode)
45 4T 4T 2T - 30 0 512T
ns ns ns ns ns ns
Output mode
2T 0 2T 8 25 16 50
ns ns ns ns
Demand release mode; m = 0 or 1
0 0 0 nT - 5 0.5T - 5 25 25
ns ns ns ns
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
135
PD70433
(2) PD70433-16
PARAMETER X1 input cycle time X1 input high-level width X1 input low-level width X1 input rise time X1 input fall time CLKOUT output cycle time CLKOUT output high-level width CLKOUT output low-level width CLKOUT output rise time CLKOUT output fall time Input rise time 12 13 Input fall time 14 Output rise time Output fall time CLKOUT delay time from X1 Address delay time from CLKOUT Address hold time (from CLKOUT) 19 Address float delay time from CLKOUT Address setup time (to ASTB) Address hold time (from ASTB) ASTB delay time from CLKOUT ASTB delay time from CLKOUT ASTB high-level width RD delay time from CLKOUT RD delay time from CLKOUT RD low-level width RD delay time from address float Address delay time from RD 20 21 22 23 24 25 26 27 28 29 30 tHKA2 tFKA tSAST tHSTA tDKSTL tDKSTH tWSTH tDKRL tDKRH tWRL tFARL tDRA 0 tHKA1 (n + 0.5)T - 25 0.5T - 15 0 0 (n + 1)T - 15 0 0 (N + 1.5)T - 15 0 0.5T 22 22 22 22 36 ns ns ns ns ns ns ns ns ns ns ns ns 15 16 118 17 18 tIF2 tOR tOF tDXK tDKA tHKA1 X2: open 5 0 *2 20 10 10 18 27 ns ns ns ns ns ns tIR2 tIF1 *2 *1 20 10 ns ns SYMBOL 1 2 3 4 5 6 7 8 9 10 11 tCYX tWXH tWXL tXR tXF tCYK tWKH tWKL tKR tKF tIR1 *1 62.5 0.5T - 5 0.5T - 5 5 5 10 TEST CONDITIONS MIN. 31.25 12 12 5 5 4000 MAX. 250 UNIT ns ns ns ns ns ns ns ns ns ns ns
n : Number of address wait states N : Number of data wait states T : tCYK * 1. Other than *2 2. RESET, P10 NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RXD0/SB1/SI0, P32/TXC/SKC0, P33/ CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 Remark Numbers in the Symbol column correspond to numbers in the timing charts.
136
PD70433
PARAMETER ASTB delay time from RD, IORD
RD, IORD delay time from WRL, WRH, IOWR
SYMBOL 119 120 31 32 33 34 35 36 37 38 39 40 41 42 43 121 122 44 45 46 47 48 tDRSTH tDWRH tDKDX tHKDX tSDK tHKDR tDKWL tDKWH tWWL tDKD tHKDW tDWSTH tDKRAL tDKRAH tWRAH tDWRAH tSARAL tSRYHK tHKRYL tSRYLK tHKRYH tWRSL1 tWRSL2 tWNIH tWNIL tSIQK tWIQH tWIQL tSPLK tSHQK tDKHA tFCHA tDHAC
TEST CONDITIONS
MIN. 0 0 0 0 11 0 0 0 (N + 1)T - 12 3 0 0 nT 0 (n + 1)T - 15 (N + 0.5)T - 10 nT - 12 18 12 18 12
MAX.
UNIT ns ns
DEX delay time from CLKOUT DEX hold time (from CLKOUT) Data input setup time (to CLKOUT) Data input hold time (from CLKOUT) WR delay time from CLKOUT WR delay time from CLKOUT WR low-level width Data output delay time from CLKOUT Data output hold time (from CLKOUT) ASTB delay time from WR RAS delay time from CLKOUT RAS delay time from CLKOUT RAS high-level width RAS delay time from WRH, WRL Address setup time (to RAS) READY setup time (to CLKOUT) READY hold time (from CLKOUT) READY setup time (to CLKOUT) READY hold time (from CLKOUT) RESET low-level width
27
ns ns ns ns
22 22
ns ns ns
27
ns ns ns
nT + 22 22
ns ns ns ns ns ns ns ns ns ms ns
STOP release/power-on reset System reset
30 1000 + 2T 5 5
49 NMI high-level width NMI low-level width INTPm setup time (to CLKOUT) INTPm high-level width INTPm low-level width POLL setup time (to CLKOUT) HLDRQ setup time (to CLKOUT) HLDAK delay time from CLKOUT HLDAK delay time from bus float Bus output delay time from HLDAK 50 51 52 53 54 55 56 57 58 59
s s
ns ns ns ns ns 27 ns ns ns
m = 0 to 5 m = 0 to 5 m = 0 to 5
25 10T 10T 25 25 0 0 T - 22.5
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
137
PD70433
PARAMETER HLDAK delay time from HLDRQ Bus output delay time from HLDRQ HLDRQ low-level width HLDAK low-level width BUSLOCK delay time from CLKOUT DMARQm setup time (to CLKOUT) DMARQm high-level width DMARQm low-level width DMARQm setup time (to CLKOUT) DMARQm low-level hold time (from CLKOUT) DMAAKm delay time from CLKOUT DMAAKm low-level width TCEm delay time from CLKOUT TCEm low-level width TOUT high-level width TOUT low-level width WDTOUT low-level width SCK cycle time
SYMBOL 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 tDHQHA tDHQC tWHQL tWHAL tDKBL tSDQK tWDQH tWDQL tSKDQ tHKDQ tDKDA tWDAL tDKTE tWTCL tWTOH tWTOL tWWTL
TEST CONDITIONS
MIN. 0.5T - 15 0.5T + 45 2T 3T - 10 0
MAX. 3.5T + 35
UNIT ns ns ns ns
27
ns ns ns ns
Except demand release mode; m = 0 or 1 Except demand release mode; m = 0 or 1 Except demand release mode; m = 0 or 1 Demand release mode; m = 0 or 1 Demand release mode; m = 0 or 1 m = 0 or 1 m = 0 or 1 m = 0 or 1 m = 0 or 1
25 2T 2T 5 12 0 (3 + n + N)T - 10 0 T - 10 8T - 10 8T - 10 32T - 10 27 27
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Input tCYSK Output Input SCK high-level width 78 tWSKH Output Input SCK low-level width SI, SB setup time (to SCK) SI, SB hold time (from SCK) 79 80 81 82 SO, SB delay time from SCK 83 SB high-level hold time (from SCK) SB low-level setup time (to SCK) SB high-level width SB low-level width 84 85 86 87 tDSKSB2 tHSKSB SBI mode tSSBSK tWSBH tWSBL SBI mode (open-drain output, RL = 1 k) tWSKL Output tSSSK tHSKS tDSKSB1 IOE mode (CMOS push-pull output)
8T 8T - 10 4T - 10 4T - 10 4T - 10 4T - 10 50 150 0 0 4T 4T 4T 4T 90 190
ns ns ns ns ns ns
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
138
PD70433
PARAMETER CTS high-level width CTS low-level width Transmit/receive data cycle TXC output clock cycle TXC output clock high-level width TXC output clock low-level width TXD delay time from TXC TXD delay time from CTS DATASTB setup time DATASTB low-level width
SYMBOL 88 89 90 91 92 93 94 95 96 97 98 tWCTH tWCTL tCYD tCYC tWCH tWCL tDTCTD tDCTTD tSDSK tWDSL1 tWDSL2 tSPDDS1 tHDSPD1 tDDSBY1 tSPDDS2 tHDSPD2 tDDSBY2 tDPDDSL tSDSAK tWAKL tSDSBY tWBYH tDKP tSPK tHKP tHSTDQ tDKREL tDKREH tDRERA tDSTLRL tWTIH tWTIL tDKT
TEST CONDITIONS
MIN. 2T 2T
MAX.
UNIT ns ns ns ns ns ns
UART
32T 32T 16T - 10
UART
16T - 10 0 90 2tCYC
ns ns ns ns
Input mode Input mode Output mode Input mode (DATASTB latch mode)
25 2T 2T - 10 45 4T 4T 512T
ns ns ns ns ns ns
PD setup time (to DATASTB) PD hold time (from DATASTB) BUSY delay time from DATASTB PD setup time (to DATASTB) PD hold time (from DATASTB) BUSY delay time from DATASTB DATASTB delay time from PD DATASTB setup time (to ACK) ACK input low-level width DATASTB setup time (to BUSY) BUSY input high-level width Port output delay time (from CLKOUT) Port input setup time (to CLKOUT) Port input hold time (from CLKOUT) DMARQm high-level hold time (from ASTB) REFRQ delay time from CLKOUT REFRQ delay time from CLKOUT RAS delay time from REFRQ RD delay time from ASTB TI high-level width TI low-level width TOm setup time (to CLKOUT)
99 100 101 102 103 104 105 106 107 108 109 123 124 125 126 127 128 129 130 131 132 133
Input mode (DATASTB latch mode)
45 4T 4T 2T - 30 0 512T
ns ns ns ns ns ns
Output mode
2T 0 2T 8 25 16 50
ns ns ns ns
Demand release mode; m = 0 or 1
0 0 0 nT - 5 0.5T - 5 4T 4T 25 25
ns ns ns ns ns ns
m = 00, 01, 20, 21, 30
5
30
ns
n : Number of address wait states N : Number of data wait states T : tCYK Remark Numbers in the Symbol column correspond to numbers in the timing charts.
139
PD70433
A/D CONVERTER CHARACTERISTICS (TA= -40 to +85 C, VDD = +5.0 V 10 %, AVSS = 0 V, VDD - 0.5 V AVDD VDD)
PARAMETER Resolution Total error *1 3.4 V AVREF AVDD 4.5 V AVREF AVDD Quantization error Conversion time tCONV 80 ns T 125 ns (for PD70433, 70433-12) 65 ns T 125 ns (for PD70433-16) 125 ns T 250 ns Sampling time tSAMP 80 ns T 125 ns (for PD70433, 70433-12) 65 ns T 125 ns (for PD70433-16) 125 ns T 250 ns Analog input voltage Analog input impedance RAN Sampling Reference voltage AVREF current AVREF AIREF T = 80 ns 3.4 1.5 *2 AVDD 5.0 V mA VIAN Non-sampling 24T -0.3 1000 AVREF + 0.3 ns V M 120T 32T ns ns 160T SYMBOL TEST CONDITIONS MIN. 8 0.8 0.6 1/2 TYP. MAX. UNIT Bit % % LSB ns
T: tCYK * 1. Excluding quantization error 2. Analog input impedance is identical with the equivalent circuit shown below. (The values in the figure are not guaranteed, but are TYP. values)
20 k Analog Input Pin 30 pF (Input Capacitance Included) 5 pF
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (TA = -40 to +85 C)
PARAMETER Data retention supply voltage Supply voltage rise time Supply voltage fall time SYMBOL
115 116 117
TEST CONDITIONS
MIN. 2.5 200 200
MAX. 5.5
UNIT V
VDDDR tRVD tFVD
s s
Remark
Numbers in the Symbol column correspond to number in the timing chart.
140
PD70433
AC Test Input Waveform *1
2.4 V 2.2 V 0.4 V 0.8 V
13
Test Points
2.2 V 0.8 V
11
* 1. Except *2 AC Test Input Waveform *2
VDD 0.8VDD 0.4 V 0.8 V
14
Test Points
0.8VDD 0.8 V
12
* 2. RESET, P10/NMI, X1, P11/INTP0 to P16/INTP5, P30/TxD0/SO0/SB0, P31/RxD0/SB1/SI0, P32/TxC/SCK0, P33/CTS0, P35/RXD1/SI1, P36/SCK1/CTS1 AC Test Output Test Points
2.2 V 0.8 V
Test Points
2.2 V 0.8 V
Load Conditions
CL = 100 pF DUT
Note
If the load capacitance exceeds 100 pF due to the configuration of the circuit, the load capacitance of this device should be reduced to 100 pF or less by insertion of a buffer, etc.
Remark
DUT: Measured device
141
PD70433
Clock Input/Output Timing
1
0.8 VDD X1 0.8 V
2 4 5 7 118 8 3
CLKOUT
2.2 V 0.8 V
9 10 6
Output Waveform (Except CLKOUT)
2.2 V 0.8 V
16
2.2 V 0.8 V
15
142
PD70433
Read Timing
T1
T2
T3
CLKOUT
17
20
A16-A23, AD8-AD15 (With 8-Bit External Bus)
19
Address
33 34
18
29
AD0-AD7, AD8-AD15 (With 16-Bit External Bus)
21
Address
Data
24
22 30
ASTB
25
23
122
42 43
RAS*1
41
130 119
26 27 30
RD, IORD
28
WRL, WRH, IOWR
31 32
DEX*2
* 1. Only activated when memory block 1 or 4 (set by the MBS register) is accessed. 2. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance.
143
PD70433
Write Timing
T1
T2
T3
CLKOUT
A16-A23, AD8-AD15 (With 8-Bit External Bus)
17
19
Address
18
38
39
AD0-AD7, AD8-AD15 (With 16-Bit External Bus)
21
Address
22
Data
24
25
ASTB
23
122
42 43
RAS*1
41
121
RD, IORD
35
40 36
WRL, WRH, IOWR
37 31
32
DEX*2
* 1. Only activated when memory block 1 or 4 (set by the MBC register) is accessed. 2. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance.
144
PD70433
Refresh Timing
T1 T2 T3
CLKOUT
20
17
19
A16-A23, AD8-AD15 (With 8-Bit External Bus)
Address
18
AD0-AD7, AD8-AD15 (With 16-Bit External Bus)
21
Address
24 22
25
ASTB
23
122
42 43
RAS
41 27
RD, IORD
36
WRL, WRH, IOWR
31 32
DEX*
129 127 128
REFRQ
*
Only valid when the external bus width is 16 bits. The dotted line indicates high-impedance.
Remark
145
PD70433
Ready Input Timing (1) 1 data wait inserted
T1 T2 TW1 T3
CLKOUT
44 45
READY
(2)
2 data waits inserted
T1 T2
47
TW1
TW2
T3
CLKOUT
45 46 44
READY
(3)
n data waits inserted (n 3)
T1
T2
TWn-2
47
TWn-1
TWn
T3
CLKOUT
45 46 44
READY
Remark
The READY input becomes valid when the corresponding field of the PWCn register (n = 0 or 1) is other than "00" (binary).
146
PD70433
DMA Timing (External Memory External I/O)
T1 T2 T3
CLKOUT
17 20 19
A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus)
Address
18
Address
24 30 22
ASTB
25
23 42
122
43
RAS *1
41 29 27
119
30
RD
130
26
28
WRL, WRH, IORD
120
35
36
IOWR
37 70 71 70
DMAAK0, DMAAK1
72
TCE0, *2 TCE1
31 73 32
DEX *3
* 1. Only activated when a DMA transfer is performed on memory block 1 or 4 (set by the MBC register). 2. The bus is activated at the last transfer in intelligent DMA mode-2, 2-channel operating mode (stop in termination), or memory-to-memory transfer mode (stop in termination). 3. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance.
147
PD70433
DMA Timing (External I/O External Memory)
T1 CLKOUT T2 T3
A16-A23, AD8-AD15 (With 8-Bit External Bus) AD0-AD7, AD8-AD15 (With 16-Bit External Bus)
17
20
19
Address
18
Address
24 30 21 22
ASTB
25
23
122
42 43
RAS *1
41
121
RD, IOWR
35
40
36
WRL, WRH
30 37 29
120
IORD
130
26 70 71
28
27 70
DMAAK0, DMAAK1
72
TCE0, *2 TCE1
73 31 32
DEX *3
* 1. Only activated when a DMA transfer is performed on memory block 1 or 4 (set by the MBC register). 2. The bus is activated at the last transfer in intelligent DMA mode-2, 2-channel operating mode (stop in termination), or memory-to-memory transfer mode (stop in termination). 3. Only valid when the external bus width is 16 bits. Remark The dotted line indicates high-impedance.
148
PD70433
INRPm Input Timing (m = 0 to 5)
CLKOUT
52 52
INTP0-INTP5
53 54
NMI Input Timing
CLKOUT
NMI
50 51
POLL Input Timing
CLKOUT
55 55
POLL
149
PD70433
DMARQm Input Timing (m = 0 or 1) (1) In demand release mode (I/O-to-memory transfer) (a) Address wait not inserted
T1 CLKOUT T2 T3 T1 T2 T3
ASTB DMAAK0, DMAAK1
70 69 70
126
68
DMARQ0, DMARQ1
68
(b)
Address wait inserted
T1 TAW T2 T3 T1 TAW T2 T3
CLKOUT
ASTB DMAAK0, DMAAK1
70 69 70
126
68
DMARQ0, DMARQ1
68
(2)
In the mode other than demand release mode
CLKOUT
65 65
DMARQ0, DMARQ1
66 67
150
PD70433
Timer Output Timing
CLKOUT
131
132
TI1
133
133
TO00, TO01, TO20 TO21, TO30
74 75
WDTOUT Output Timing
WDTOUT
76
BUSLOCK Output Timing
CLKOUT
64 64
BUSLOCK
Data Retention Timing (STOP Mode)
VDD
117
115
116
151
PD70433
Hold Request/Acknowledge Timing (1) In normal mode
CLKOUT
56 56
HLDRQ
57
62
Bus Control Signal*
58 60
Hi-Z
59
HLDAK
63
*
ASTB, RD, WRH, WRL, DEX, RAS, BUSLOCK, IORD, IOWR, AD0 to AD15, A16 to A23 (2) Release of hold mode for refresh cycle insertion
CLKOUT
56
HLDRQ
62
Bus Control Signal*
Hi-Z
57 61
HLDAK
*
ASTB, RD, WRH, WRL, DEX, RAS, BUSLOCK, IORD, IOWR, AD0 to AD15, A16 to A23
152
PD70433
RESET Input Timing (1) STOP mode release/power-on reset
CLKOUT
48
RESET
(2)
System reset
CLKOUT
49
RESET
CTSm Input Timing (m = 0 or 1)
CTS0, CTS1
88 89
153
PD70433
Serial Interface Timing (1) 3-wire serial I/O mode
79
78
SCK0, SCK1
77 80 81
SI0, SI1
82
Input Data
SO0, SO1
Output Data
(2)
SBI mode Bus release signal transfer timing
SCK0
84 87 86 85
SB0, SB1
Command signal transfer timing
79 78
SCK0
84 85 77 83 80 81
SB0, SB1
Input/Output Data
154
PD70433
(3)
UART mode Transmit timing
91 93 92
TxC
94 90
TxD0
Output Data
90
TxD1
Output Data
Receive timing
90
RxD0, RxD1
Input Data
Transmission enale timing
CTS0, CTS1
95
TxD0, TxD1
Start Bit
155
PD70433
Parallel Interface Timing (1) Input mode
CLKOUT
96
97
DATASTB
99 102
100 103
PD0-PD7
Input Data
104 101
BUSY
(2)
Output mode
DATASTB
105 98
PD0-PD7
106
Output Data
107
ACK
108
BUSY
109
156
PD70433
Port Input/Output Timing
T2/TI CLKOUT
124
T3
T1/TI
Input Port
125
Output Port
123
157
PD70433
19. CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
IOH vs (VDD - VOH)
-3.0 (TA = 25 C, VDD = 5.0 V)
High-Level Output Current IOH [mA]
-2.0
-1.0
0 0 0.2 0.4 0.6 VDD - VOH [V]
Supply Voltage - High-Level Output Voltage
IOL vs VOL
6.0 (TA = 25 C, VDD = 5.0 V)
Low-Level Output Current I OL [mA]
4.0
2.0
0 0 0.2 Low-Level Output Voltage 0.4 VOL [V] 0.6
158
PD70433
20. PACKAGE DRAWINGS
120 PIN PLASTIC QFP (
28)
A B
90 91
61 60
detail of lead end
D
C
S
120 1
31 30
F
G
H
IM
J K
P
N L
M
P120GD-80-5BB-3 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 32.0 0.4 28.0 0.2 28.0 0.2 32.0 0.4 2.4 2.4 0.35 0.10 0.15 0.8 (T.P.) 2.0 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 3.7 0.1 0.1 4.0 MAX. INCHES 1.260 0.016 1.102+0.009 -0.008 1.102+0.009 -0.008 1.260 0.016 0.094 0.094 0.014 +0.004 -0.005 0.006 0.031 (T.P.) 0.079 -0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.146 0.004 0.004 0.157 MAX.
+0.009
55
Q
159
PD70433
120 PIN PLASTIC QFP (FINE PITCH) (
A B
20)
90 91
61 60 detail of lead end
C
D
S
120
31 1 30
F
G
H
I
M
J K
P
N
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 22.00.2 20.00.2 20.00.2 22.00.2 2.75 2.75 0.22 +0.05 -0.04 0.10 0.5 (T.P.) 1.00.2 0.50.2 0.17 +0.03 -0.07 0.10 2.7 0.1250.075 55 3.0 MAX. INCHES 0.8660.008 0.787 +0.009 -0.008 0.787 +0.009 -0.008 0.8660.008 0.108 0.108 0.0090.002 0.004 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.004 0.106 0.0050.003 55 0.119 MAX. S120GJ-50-3EB-2
NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition.
160
M
Q
R
PD70433
132 PIN CERAMIC PGA
A (Bottom View) 14 13 12 11 10 9 8 7 6 5 4 3 2 1 P NML K J HG F EDC B A Index mark J I Orientation pin
G
H
K L
E
M M
F X132R-100A-1
NOTE Each lead centerline is located within 0.5 mm ( 0.020 inch) of its true position (T.P.) at maximum material condition.
D ITEM A D E F G H I J K L M
MILLIMETERS 35.56 0.3 35.56 0.3 1.27 2.54 (T.P.) 2.8 0.3 0.9 MIN. 2.95 4.57 MAX.
INCHES 1.400 0.012 1.400 0.012 0.050 0.100 (T.P.) 0.110 0.012 0.035 MIN. 0.116 0.180 MAX.
1.2 0.2 0.46 0.05
0.254
0.047+0.009 -0.008 0.018 0.002
0.010
161
PD70433
21. RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting Technology Manual" (C10535E). For soldering methods and conditions other than those recommended, contact our sales personnel. Table 21-1. Surface Mount Type Soldering Conditions (1) PD70433GD-xx-5BB : 120-Pin Plastic QFP (28 x 28 mm)
Soldering Method Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Within twice, Time limit: 7 days* (thereafter 36 hours 125 C prebanking required) Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Within twice, Time limit: 7 days* (thereafter 36 hours 125 C prebanking required) Solder bath temperature: 260 C or less, Time: 10 sec. max., Number of times: Once, Time limit: 7 days* (thereafter 35 hours 125 C prebanking required), Preheating temperature: 120 C max. (Package surface temperature) Pin temperature: 300 C or below, Duration: 3 sec. max. (per pin row) Recommended Condition Symbol IR35-367-2
Infrared reflow
VPS
VP15-367-2
Wave soldering
WS60-367-1
Partial heating
---
*
For the storage period after dry-pack decompression, storage conditions are max. 25 C, 65 % RH. Use of more than one soldering method should be avoided (except in the case of partial heating method).
Note
(2) PD70433GJ-xx-3EB : 120-Pin Plastic QFP (Fine Pitch) (20 x 20 mm)
Recommended Condition Symbol IR35-00-2 VP15-00-2 ---
Soldering Method Infrared reflow VPS Partial heating
Soldering Conditions Package peak temperature: 235 C, Duration: 30 sec. max. (at 210 C or above), Number of times: Within twice Package peak temperature: 215 C, Duration: 40 sec. max. (at 200 C or above), Number of times: Within twice Pin temperature: 300 C or below, Duration: 3 sec. max. (per pin row)
Note
Use of more than one soldering method should be avoided (except in the case of partial heating method).
Table 21-2. Insertion Type Soldering Conditions
PD70433R-xx : 132-Pin Ceramic PGA
Soldering Method Wave soldering (lead part only) Partial heating Soldering Conditions Solder temperature: 260 C or less, Duration: 10 sec. max. Pin temperature: 300 C or less, Duration: 3 sec. max. (per pin row)
Note
Wave soldering is used on the lead part only, and care must be taken to prevent solder from coming into direct contact with the body.
162
PD70433
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290
NEC Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
NEC Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96. 8
163
PD70433
[MEMO]
164
PD70433
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
165
PD70433
[MEMO]
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. V20, V30, V25, V35, V25+, V55PI are trademarks of NEC Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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